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written in SystemVerilog
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OpenTitan: Open source silicon root of trust
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Common SystemVerilog components
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
Vector processor for RISC-V vector ISA
FPGA based Vision Transformer accelerator (Harvard CS205)
