A RISC-V doubly-linked list. nd24sp-arch-hw4-report.pdf explains how step iterates on the problem and dllist_final.S contains the final product.
In summary, the final assembly file:
- allocates the necessary memory for several nodes of a dllist
- inputs data into that dllist
- selectively deletes a node from the dllist
- frees all data from memory
The project was tested using Cornell's RISC-V Interpreter, on which this code will run as described. There you can view all the registers and memory addresses as they update in real time.
The project received 1970/2000 possible points. The grading rubric can be found here.
The project was created for CSE 30321: Computer Architecture in the spring semester of 2024.
dllist_step1.Sdllist_step2.Sdllist_step3.Sdllist_step4.Sdllist_final.Snd24sp-arch-hw4-report.pdf