Reorganize POWER9 SIMD code #369
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Yes - good point. I have to update |
ggerganov
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Yes, I don't have any changes left to push. Thanks for reviewing and testing the patch set. |
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I could not eliminate the separate index argument in the f16 load and store macros, so this patch set needs testing on other architectures.
The existing GGML_F32x4_REDUCE macro performs as well as the implementation in #366 so I used the existing one.
When I test with the F32 model, ggml_vec_dot_f16 and ggml_vec_mad_f16 are still being called. Is that expected?