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This PR adds an associated index for the CUDA and HIP backends. This prevents a runtime failure when trying to target these two vendors. As currently the Nvidia build fails to run in these cases.
This PR adds an associated index for the CUDA and HIP backends. This prevents a runtime failure when trying to target these two vendors. As currently the Nvidia build fails to run in these cases.
Tested on A100 and PVC
Due to the code have AMD branch, it's better to verify on AMD GPU to cover this branch.
Is it possible to test on AMD too?
This PR adds an associated index for the CUDA and HIP backends. This prevents a runtime failure when trying to target these two vendors. As currently the Nvidia build fails to run in these cases.
Tested on A100 and PVC
Due to the code have AMD branch, it's better to verify on AMD GPU to cover this branch. Is it possible to test on AMD too?
I have verified it on AMD GPU as well, specifically the MI210.
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This PR adds an associated index for the CUDA and HIP backends. This prevents a runtime failure when trying to target these two vendors. As currently the Nvidia build fails to run in these cases.
Tested on A100 and PVC