Design and implementation of RISC-V processor with a pipelined datapath, controller, and hazard unit.
R_Type: add, sub, and, or, sltI_Type: lw, addi, xori, ori, slti, jalrS_Type: swJ_Type: jalB_Type: beq, bne, blt, bgeU_Type: lui
The following assembly code can be converted to machine code using RISC-V Online Assembler.
addi X7,X0,16;
addi X8,X0,30;
sub X9,X8,X7;
and X10,X8,X7;
or X11,X8,X7;
slt X12,X8,X7;
xori X13,X7,13;
ori X14,X7,13;
slti X15,X7,13;
sw X8,400(x7);
lui X17,60;
jalr X16,X7,10;- Course: Digital Systems 2 [ECE 778]
- Semester: Spring 2023
- Institution: School of Electrical & Computer Engineering, College of Engineering, University of Tehran
- Instructors: Dr. Safari
- Contributors: Fardin Abbasi, Soheil Abdollahi