rga: ripgrep, but also search in PDFs, E-Books, Office documents, zip, tar.gz, etc.

Automatically exported from code.google.com/p/xtreamerdev

I2C controller core

Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)

GPIO IP core from opencores.

Example for accessing low level RISC-V hardware with C

RISC-V CSR Access Routines

Opensource DDR3 Controller

Universal utility for programming FPGA

An Open Source configuration of the Arty platform

A set of Wishbone Controlled SPI Flash Controllers

RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K

BoxLamba fork of pbing's USB repo.

usb_hid_host fork for BoxLambda

Forth CPU J1 in SystemVerilog and Wishbone interface

J1 Forth cross compiler

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

FPGA USB 1.1 Low-Speed Implementation

Getting to space with kOS!

FPGA based microcomputer sandbox for software and RTL experimentation

USB Host Dual Socket Pmod™ Compatible Module

ps2 keyboard and mouse driver for stm32

Interfaz directa con teclados USB en Verilog con control de los Leds de teclado y conversión a PS/2.

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端…

Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs

Basic USB-CDC device core (Verilog)

USB Full Speed PHY

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

PicoRV32 - A Size-Optimized RISC-V CPU

Chromaprint + fpcalc + python + statistics = compare audio files and determine similarity