Merge pull request intel#188 from edwarddavidbaker/sync-platforms

SRF, GRR, EMR, SPR, MTL: Release event updates
edwarddavidbaker · May 22, 2024 · abd4922 · abd4922
2 parents 763ec2e + 0a9546c
commit abd4922
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Showing 17 changed files with 1,484 additions and 980 deletions.
diff --git a/EMR/events/emeraldrapids_core.json b/EMR/events/emeraldrapids_core.json
@@ -1,9 +1,9 @@
 {
  "Header": {
  "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
- "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.08",
- "DatePublished": "04/01/2024",
- "Version": "1.08",
+ "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.09",
+ "DatePublished": "05/21/2024",
+ "Version": "1.09",
  "Legend": ""
  },
  "Events": [
@@ -787,6 +787,58 @@
  "PDISTCounter": "0",
  "Speculative": "1"
  },
+ {
+ "EventCode": "0x20",
+ "UMask": "0x02",
+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
+ "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
+ "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
+ "Counter": "0,1,2,3",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "MSRIndex": "0x00",
+ "MSRValue": "0x00",
+ "Precise": "0",
+ "CollectPEBSRecord": "2",
+ "TakenAlone": "0",
+ "CounterMask": "1",
+ "Invert": "0",
+ "EdgeDetect": "0",
+ "PEBS": "0",
+ "Data_LA": "0",
+ "L1_Hit_Indication": "0",
+ "Errata": "null",
+ "Offcore": "0",
+ "Deprecated": "0",
+ "PDISTCounter": "0",
+ "Speculative": "1"
+ },
+ {
+ "EventCode": "0x20",
+ "UMask": "0x02",
+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
+ "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
+ "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
+ "Counter": "0,1,2,3",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "MSRIndex": "0x00",
+ "MSRValue": "0x00",
+ "Precise": "0",
+ "CollectPEBSRecord": "2",
+ "TakenAlone": "0",
+ "CounterMask": "0",
+ "Invert": "0",
+ "EdgeDetect": "0",
+ "PEBS": "0",
+ "Data_LA": "0",
+ "L1_Hit_Indication": "0",
+ "Errata": "null",
+ "Offcore": "0",
+ "Deprecated": "0",
+ "PDISTCounter": "0",
+ "Speculative": "1"
+ },
  {
  "EventCode": "0x20",
  "UMask": "0x04",
@@ -943,6 +995,58 @@
  "PDISTCounter": "0",
  "Speculative": "1"
  },
+ {
+ "EventCode": "0x21",
+ "UMask": "0x02",
+ "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
+ "BriefDescription": "Cacheable and noncacheable code read requests",
+ "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
+ "Counter": "0,1,2,3",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "100003",
+ "MSRIndex": "0x00",
+ "MSRValue": "0x00",
+ "Precise": "0",
+ "CollectPEBSRecord": "2",
+ "TakenAlone": "0",
+ "CounterMask": "0",
+ "Invert": "0",
+ "EdgeDetect": "0",
+ "PEBS": "0",
+ "Data_LA": "0",
+ "L1_Hit_Indication": "0",
+ "Errata": "null",
+ "Offcore": "0",
+ "Deprecated": "0",
+ "PDISTCounter": "0",
+ "Speculative": "1"
+ },
+ {
+ "EventCode": "0x21",
+ "UMask": "0x04",
+ "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
+ "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
+ "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
+ "Counter": "0,1,2,3",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "100003",
+ "MSRIndex": "0x00",
+ "MSRValue": "0x00",
+ "Precise": "0",
+ "CollectPEBSRecord": "2",
+ "TakenAlone": "0",
+ "CounterMask": "0",
+ "Invert": "0",
+ "EdgeDetect": "0",
+ "PEBS": "0",
+ "Data_LA": "0",
+ "L1_Hit_Indication": "0",
+ "Errata": "null",
+ "Offcore": "0",
+ "Deprecated": "0",
+ "PDISTCounter": "0",
+ "Speculative": "1"
+ },
  {
  "EventCode": "0x21",
  "UMask": "0x08",
@@ -1021,6 +1125,32 @@
  "PDISTCounter": "0",
  "Speculative": "1"
  },
+ {
+ "EventCode": "0x23",
+ "UMask": "0x40",
+ "EventName": "L2_TRANS.L2_WB",
+ "BriefDescription": "L2 writebacks that access L2 cache",
+ "PublicDescription": "Counts L2 writebacks that access L2 cache.",
+ "Counter": "0,1,2,3",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "200003",
+ "MSRIndex": "0x00",
+ "MSRValue": "0x00",
+ "Precise": "0",
+ "CollectPEBSRecord": "2",
+ "TakenAlone": "0",
+ "CounterMask": "0",
+ "Invert": "0",
+ "EdgeDetect": "0",
+ "PEBS": "0",
+ "Data_LA": "0",
+ "L1_Hit_Indication": "0",
+ "Errata": "null",
+ "Offcore": "0",
+ "Deprecated": "0",
+ "PDISTCounter": "0",
+ "Speculative": "1"
+ },
  {
  "EventCode": "0x24",
  "UMask": "0x21",
@@ -1571,8 +1701,8 @@
  "EventCode": "0x26",
  "UMask": "0x02",
  "EventName": "L2_LINES_OUT.NON_SILENT",
- "BriefDescription": "L2_LINES_OUT.NON_SILENT",
- "PublicDescription": "L2_LINES_OUT.NON_SILENT",
+ "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
+ "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
  "Counter": "0,1,2,3",
  "PEBScounters": "0,1,2,3",
  "SampleAfterValue": "200003",
@@ -2789,6 +2919,32 @@
  "PDISTCounter": "0",
  "Speculative": "1"
  },
+ {
+ "EventCode": "0x80",
+ "UMask": "0x04",
+ "EventName": "ICACHE_DATA.STALL_PERIODS",
+ "BriefDescription": "ICACHE_DATA.STALL_PERIODS",
+ "PublicDescription": "ICACHE_DATA.STALL_PERIODS",
+ "Counter": "0,1,2,3",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "500009",
+ "MSRIndex": "0x00",
+ "MSRValue": "0x00",
+ "Precise": "0",
+ "CollectPEBSRecord": "2",
+ "TakenAlone": "0",
+ "CounterMask": "1",
+ "Invert": "0",
+ "EdgeDetect": "1",
+ "PEBS": "0",
+ "Data_LA": "0",
+ "L1_Hit_Indication": "0",
+ "Errata": "null",
+ "Offcore": "0",
+ "Deprecated": "0",
+ "PDISTCounter": "0",
+ "Speculative": "1"
+ },
  {
  "EventCode": "0x83",
  "UMask": "0x04",
@@ -3985,6 +4141,32 @@
  "PDISTCounter": "0",
  "Speculative": "1"
  },
+ {
+ "EventCode": "0xae",
+ "UMask": "0x01",
+ "EventName": "UOPS_ISSUED.CYCLES",
+ "BriefDescription": "UOPS_ISSUED.CYCLES",
+ "PublicDescription": "UOPS_ISSUED.CYCLES",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "SampleAfterValue": "2000003",
+ "MSRIndex": "0x00",
+ "MSRValue": "0x00",
+ "Precise": "0",
+ "CollectPEBSRecord": "2",
+ "TakenAlone": "0",
+ "CounterMask": "1",
+ "Invert": "0",
+ "EdgeDetect": "0",
+ "PEBS": "0",
+ "Data_LA": "0",
+ "L1_Hit_Indication": "0",
+ "Errata": "null",
+ "Offcore": "0",
+ "Deprecated": "0",
+ "PDISTCounter": "0",
+ "Speculative": "1"
+ },
  {
  "EventCode": "0xb0",
  "UMask": "0x01",
@@ -6949,6 +7131,32 @@
  "PDISTCounter": "NA",
  "Speculative": "0"
  },
+ {
+ "EventCode": "0xcd",
+ "UMask": "0x01",
+ "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024",
+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.",
+ "Counter": "1,2,3,4,5,6,7",
+ "PEBScounters": "1,2,3,4,5,6,7",
+ "SampleAfterValue": "53",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x400",
+ "Precise": "1",
+ "CollectPEBSRecord": "2",
+ "TakenAlone": "1",
+ "CounterMask": "0",
+ "Invert": "0",
+ "EdgeDetect": "0",
+ "PEBS": "2",
+ "Data_LA": "1",
+ "L1_Hit_Indication": "0",
+ "Errata": "null",
+ "Offcore": "0",
+ "Deprecated": "0",
+ "PDISTCounter": "NA",
+ "Speculative": "0"
+ },
  {
  "EventCode": "0xcd",
  "UMask": "0x02",

diff --git a/EMR/events/emeraldrapids_uncore.json b/EMR/events/emeraldrapids_uncore.json
@@ -1,9 +1,9 @@
 {
  "Header": {
  "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
- "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.08",
- "DatePublished": "04/01/2024",
- "Version": "1.08",
+ "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.09",
+ "DatePublished": "05/21/2024",
+ "Version": "1.09",
  "Legend": ""
  },
  "Events": [

diff --git a/EMR/events/emeraldrapids_uncore_experimental.json b/EMR/events/emeraldrapids_uncore_experimental.json
@@ -1,9 +1,9 @@
 {
  "Header": {
  "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
- "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.08",
- "DatePublished": "04/01/2024",
- "Version": "1.08",
+ "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.09",
+ "DatePublished": "05/21/2024",
+ "Version": "1.09",
  "Legend": ""
  },
  "Events": [