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1. dubcyfor3 dubcyfor3 Public

   Config files for my GitHub profile.

   1

2. gnn-acceleration-framework-with-FPGA gnn-acceleration-framework-with-FPGA Public

   Forked from I-Doctor/gnn-acceleration-framework-with-FPGA

   including compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware verilog code that can be implemented on FPGA

   SystemVerilog

3. handy_graph handy_graph Public

   Forked from fuvty/handy_graph

   A collection of frequently-used functions based on networkx

   Python

4. RTL_library_of_basic_hardware_units RTL_library_of_basic_hardware_units Public

   Forked from I-Doctor/RTL_library_of_basic_hardware_units

   Here are some implementations of some basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and support the hardware design tradeoff.

   Verilog

5. actnn actnn Public

   Forked from ucbrise/actnn

   ActNN: Reducing Training Memory Footprint via 2-Bit Activation Compressed Training

   Python