This collaborative project, completed as part of Cornell University's ECE 5760 course under the guidance of Professor V. Hunter Adams, was a joint effort by Keyun Gao, Yen-An Lu, and Dengyu (Spud) Tu. The team successfully designed and implemented a FPGA accelerated Sudoku Puzzle Solver.

This project aims to solve Sudoku puzzles using Field-Programmable Gate Array (FPGA) technology, providing users with an elegant interface for interacting with the Sudoku grid. Sudoku puzzles are not only entertaining but also offer cognitive benefits such as problem-solving and critical thinking. Leveraging the rapid processing capabilities of FPGA, this project hopes to create an engaging platform for Sudoku enthusiasts to enjoy and improve their skills.

Technical Details:

• Hardware Component: Intel DE1-SoC, VGA display, Micro SD card, Keyboard, Mouse.
• Programming Language: Verilog, C

For comprehensive information on the project, including design details, implementation techniques, and results, visit the Project Webpage.

A visual representation of the project's capabilities is showcased in the Video Demonstration.

The project repository includes:

• Multiple C files responsible for functions such as receiving user input, rendering graphics on the VGA display, managing game controls, and transmitting data to the VGA.
• Verilog files dedicated to implementing the hardware solver for Sudoku puzzles.
• DE1 file designed to configure the FPGA and establish connections with the VGA display.

1. Connect Components: Connect the SoC platform with the VGA display (Caution: our VGA pixel clock runs around 25 MHz. If your VGA clock runs at differnt frequency, you might need to configure the DE1_SoC_Computer file yourself.)
2. Load Linux Image: Load this Linux image onto the Micro SD card. (Windows User: use software like Win32 Disk Imager. Mac User: use software like ApplePiBaker.)
3. Clone Repository: Clone the repository to your local machine.
4. Unzip Folder: Unzip the FPGA+VGA_Final.zip file inside the DE1 folder.
5. Compile Verilog Code: Compile the DE1_SoC_Computer.qar file which is inside the computer_640_16bit_video/verilog folder using your preferred FPGA development environment. (We used Quartus.)
6. Upload Bitstream: Upload the generated bitstream to your FPGA board.
7. Upload C file: Upload the Final.c file which is inside the C folder to your Micro SD card.
8. Compile C Code: Compile the Final.c file with command Final.c -o Final -O2 -lm .
9. Run Application: Run the application on Linux with terminal command ./Final /dev/input/eventx (where x depends on the event number of the keyboard in Linux).

We would like to thank Cornell University's ECE 5760 course for providing the Linux image and the computer_640_16bit_video file.

This project is licensed under the MIT License.