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OpenTimer Public
Forked from OpenTimer/OpenTimerA High-performance Timing Analysis Tool for VLSI Systems
Verilog Other UpdatedDec 28, 2022 -
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iic-audiodac-v1 Public
Forked from iic-jku/iic-audiodac-v1Delta-sigma audio DAC (16b, 48kHz), intended for tape-out on MPW-5, SKY130 technology.
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This is a repository containing all the Quartus and NIOS II simulation files and the testcases for EE705 course
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my8085 Public
This is the Verilog code for 8085 microprocessor with limited (18) number of instructions
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IITB-Campus-Placement-Resumes Public
Forked from SudhakarKuma/IITB-Campus-Placement-ResumesUpdatedJul 4, 2021 -
This is a verilog implementation of 4x4 systolic array multiplier
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biriscv Public
Forked from ultraembedded/biriscv32-bit Superscalar RISC-V CPU
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pipelinedcustomrisc Public
Verilog implementation of a 6-stage pipelined custom RISC processor
C MIT License UpdatedJul 31, 2020 -
customrisc Public
This is the Verilog implementation of custom RISC ISA
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fpga_counter_spartan6 Public
FPGA implementation of up / down BCD counter
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booth_multiplier Public
Verilog Implementation of completely parameterized booth multiplier
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des_crypto Public
This is the verilog implementation of DES cryptography
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fmultiplier Public
This is the verilog implementation of IEEE 754 32 bit floating point multiplier
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Superscalar-MIPS Public
Forked from GeekAlexis/superscalar-mipsA MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines
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rodinia Public
Forked from qbunia/rodiniarodinia benchmark modified to run with ENZO and pathcu instead of nvcc CUDA compiler
C Other UpdatedApr 9, 2013