We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.
You must be logged in to block users.
Contact GitHub support about this user’s behavior. Learn more about reporting abuse.
synthesiseable ieee 754 floating point library in verilog
Verilog 521 142
FPGA Design Suite based on C to Verilog design flow.
Python 231 47
Build a SDR SW/MW/LW Receiver with a Raspberry Pi Pico
C 223 30
A collection of cool projects to make!
G-code 134 18
FPGA based transmitter
Verilog 89 14
Mathematical Functions in Verilog
Verilog 84 26