Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

AMBA bus lecture material

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

A minimal GPU design in Verilog to learn how GPUs work from the ground up

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

Build your hardware, easily!

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

This repository is used to release the Labs of Computer Architecture Course from USTC

An open source FPGA PCI core & 8250-Compatible PCI UART core

USB Full Speed PHY

FPGA implementation of deflate (de)compress RFC 1950/1951

A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs

Basic Peripheral SoC (SPI, GPIO, Timer, UART)

Real time face detection based on Arm Cortex-M3 DesignStart and FPGA

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Verilog SDRAM memory controller

Verilog Ethernet components for FPGA implementation

PicoRV32 - A Size-Optimized RISC-V CPU

Various HDL (Verilog) IP Cores

32-bit Superscalar RISC-V CPU

synthesiseable ieee 754 floating point library in verilog

A simple, basic, formally verified UART controller

Simple 8-bit UART realization on Verilog HDL.

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

Opensource DDR3 Controller

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

IC design and development should be faster，simpler and more reliable

Must-have verilog systemverilog modules

A FPGA friendly 32 bit RISC-V CPU implementation