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Школа Синтеза Цифровых Схем

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  1. systemverilog-homework systemverilog-homework Public

    Forked from yuri-panchul/systemverilog-homework

    SystemVerilog language-oriented exercises

    SystemVerilog 29 19

  2. basics-graphics-music basics-graphics-music Public

    Forked from yuri-panchul/basics-graphics-music

    FPGA exercise for beginners

    SystemVerilog 20 11

  3. audio_synth_practice audio_synth_practice Public

    Forked from Konf/audio_synth_practice

    SystemVerilog 1 2

  4. synth_school_verif_tasks synth_school_verif_tasks Public

    Forked from serge0699/synth_school_verif_tasks

    SystemVerilog 1

  5. miriscv miriscv Public

    Forked from Konf/miriscv_dds

    Assembly

  6. schoolRISCV_ICache schoolRISCV_ICache Public

    Forked from NickolayTernovoy/schoolRISCV_ICache

    Академический проект для исследования прироста производительности процессора в зависимости от конфигурации Иерархии Памяти

    Makefile

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