added standalone UART Test

2.Simple--5--UART-Test/1.hw/top.sv

@@ -0,0 +1,96 @@
+//======================================================================== 
+// openCologne * NLnet-sponsored open-source design ware for GateMate
+//------------------------------------------------------------------------
+// Copyright (C) 2024 Chili.CHIPS*ba
+// 
+// Redistribution and use in source and binary forms, with or without 
+// modification, are permitted provided that the following conditions 
+// are met:
+//
+// 1. Redistributions of source code must retain the above copyright 
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright 
+// notice, this list of conditions and the following disclaimer in the 
+// documentation and/or other materials provided with the distribution.
+//
+// 3. Neither the name of the copyright holder nor the names of its 
+// contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// https://opensource.org/license/bsd-3-clause
+//------------------------------------------------------------------------
+// Description: <your text goes here>
+//========================================================================
+
+// <modify as needed>
+
+module top 
+ import top_pkg::*;
+(
+ input logic areset, // external active-1 asynchronous reset
+ input logic clk_ext, // external 100MHz clock source
+
+ //I2C_Master to Camera
+ inout wire i2c_sda,
+ inout wire i2c_scl,
+
+ //MIPI DPHY from/to Camera
+ input diff_t cam_dphy_clk,
+ input lane_diff_t cam_dphy_dat
+);
+
+//--------------------------------
+// Clock and reset gen
+//--------------------------------
+ logic reset, i2c_reset;
+ logic clk_100, clk_200, clk_1hz, strobe_400kHz;
+
+ clkrst_gen u_clkrst_gen (
+ .reset_ext (areset), //i
+ .clk_ext (clk_ext), //i
+
+ .clk_100 (clk_100), //o: 100MHz 
+ .clk_200 (clk_200), //o: 200MHz 
+ .clk_1hz (clk_1hz), //o: 1Hz
+ .strobe_400kHz (strobe_400kHz), //o: pulse1 at 400kHz
+
+ .reset (reset), //o
+ .cam_en (cam_en), //o
+ .i2c_reset (i2c_reset) //o
+ );
+
+//--------------------------------
+// I2C Master
+//--------------------------------
+ i2c_top u_i2c (
+ //clocks and resets
+ .clk (clk_100), //i
+ .strobe_400kHz (strobe_400kHz), //i
+ .reset (i2c_reset), //i
+
+ //I2C_Master to Camera
+ .i2c_scl (i2c_scl), //io 
+ .i2c_sda (i2c_sda) //io 
+ );
+
+endmodule: top
+
+/*
+------------------------------------------------------------------------------
+Version History:
+------------------------------------------------------------------------------
+ 2024/5/10 <your-name>: Initial creation
+*/

2.Simple--5--UART-Test/2.sim/.gtkwaverc

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+[*]
+[*] GTKWave Analyzer v3.3.118 (w)1999-2023 BSI
+[*] Sat Apr 20 07:43:13 2024
+[*]
+[dumpfile] "/mnt/d/Projects/GitHub-repo/eduSOC/4.sim/output/wave.fst"
+[dumpfile_mtime] "Sat Apr 20 06:25:58 2024"
+[dumpfile_size] 31441595
+[savefile] "/mnt/d/Projects/GitHub-repo/eduSOC/4.sim/.gtkwaverc"
+[timestart] 2
+[size] 1380 793
+[pos] -1 -1
+*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] TOP.
+[treeopen] TOP.tb.
+[treeopen] TOP.tb.dut.
+[sst_width] 214
+[signals_width] 319
+[sst_expanded] 1
+[sst_vpaned_height] 220
+[pattern_trace] 1
+[pattern_trace] 0

2.Simple--5--UART-Test/2.sim/Makefile

@@ -0,0 +1,118 @@
+#=============================================================
+# Copyright (C) 2024 Chili.CHIPS*ba
+#=============================================================
+SHELL := /bin/bash
+
+HW_SRC := $(CURDIR)/../1.hw
+TB_NAME := tb
+
+export HW_SRC TB_NAME
+
+
+#------------------------
+.PHONY: all
+all: clean sim wave
+
+#------------------------
+clean:
+ rm -rf output
+
+#-------------------------------------------------------------
+#___Global macros___
+# +define+SIM_ONLY \ to speed-up things for sim
+# +define+MIPI_4_LANE \
+#
+#___Xilinx macros___
+# +define+XIL_TIMING \
+# +define+HACKED_UNISIM \
+#
+#-------------------------------------------------------------
+compile: 
+ verilator \
+ --cc \
+ --timing \
+ --trace-fst \
+ --trace-structs \
+ --timescale-override 1ps/1ps \
+ --exe versimSV.cpp \
+ --Mdir ./output \
+ \
+ +define+SIM_ONLY \
+ +define+HACKED_UNISIM \
+ \
+ -f ${HW_SRC}/top.filelist \
+ \
+ models/xilinx.unisim.CHILI.v \
+ ${TB_NAME}.sv \
+ --top-module ${TB_NAME}
+
+# -O1 \
+# -O3 \
+# -Wno-fatal \
+# --debug \
+# --trace-threads 1 \
+#
+# --x-assign fast \
+# --x-initial fast \
+# --noassert \
+# --no-timing \
+# --trace-depth 10 \
+# --trace-max-array 1024 \ Maximum array depth for tracing
+# --trace-max-width 32 \ Maximum bit width for tracing
+#
+# --assert \ read //synopsys full_case or //synopsys parallel_case
+# //ambit synthesis, //cadence or //pragma directives
+# Also asserts any "unique" or "priority" SV keywords on
+# case statements, as well as "unique" on if statements.
+# However, "priority if" is currently ignored.
+
+
+#------------------------
+sim: compile
+ cd output; \
+ make -f V${TB_NAME}.mk V${TB_NAME}; \
+ ./V${TB_NAME} | tee sim.log
+
+#------------------------
+wave: xml2stems
+ cd output; \
+ gtkwave --saveonexit \
+ --slider-zoom \
+ --stems ../tb.stems \
+ --logfile sim.log \
+ -rc ../.gtkwaverc \
+ --dump wave.fst &
+
+# --wish \
+# --save ../wave.gtkw 
+
+#------------------------
+wave-alt: 
+ cd output; \
+ surfer.exe -s ../wave.surfer.ron wave.fst &
+
+#------------------------
+xml2stems: 
+ verilator \
+ --timing \
+ -xml-only \
+ -xml-output tb.xml \
+ --timescale 1ps/1ps \
+ -f ${HW_SRC}/top.filelist \
+ ${TB_NAME}.sv \
+ \
+ +define+SIM_ONLY \
+ +define+HACKED_UNISIM \
+ \
+ models/xilinx.unisim.CHILI.v \
+ --top-module ${TB_NAME}
+ xml2stems tb.xml tb.stems
+
+
+#------------------------
+rtlbrowse: xml2stems
+ rtlbrowse tb.stems 
+
+#=============================================================
+# End-of-File
+#=============================================================