Specification of the Programming Design and Verification Language (PDVL)

The cephalopod IoT processor and the bifrost compiler

An open bibliography of machine learning for formal proof papers

The source code to the Voss II Hardware Verification Suite

A hardware synthesis framework with multi-level paradigm

Formal specification and verification of hardware, especially for security and privacy.

A formally verified high-level synthesis tool based on CompCert and written in Coq.

A Haskell to HDL (Verilog/VHDL) Compiler

A modern schematic entry and simulation program

Interactive Coq Proofs in Vim

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

A modular build system for hardware

A collection of common Bluespec interfaces/modules.

Intermediate Language (IL) for Hardware Accelerator Generators

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

XLS: Accelerated HW Synthesis

A core language for rule-based hardware design 🦑

Scots Army Knife for electronics

RTL implementation of components for DVB-S2

A modern hardware definition language and toolchain based on Python

Bluespec Compiler (BSC)

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

Read-only mirror of https://gitlab.gnome.org/GNOME/dia

UVM 1.2 port to Python

draw.io is a JavaScript, client-side editor for general diagramming.

Unit testing for cocotb

A Python package for testing hardware (part of the magma ecosystem)

CoreIR Symbolic Analyzer

VHDL compiler and simulator