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FPGA debug
unlockedOscillator edited this page Mar 15, 2017
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All JTAG-capable FPGAs we're aware of support at least 2 instructions (USER1/USER2)
We define the following discovery protocol for runtime in-system debug over JTAG.
This register is a 32-bit read-only value hard-wired at implementation time.
- VENDOR_ID (DEBUG_IDCODE[31:8]): Identifies the person or organization who specified this debug protocol. This is not necessarily the implementer of the interface core or the SoC vendor.
- PROTO_ID (DEBUG_IDCODE[7:0]): Identifies the particular debug protocol and version of the core in use.
The meaning and functionality of this register are specified by the specific debug protocol in use.
- 24'h42445A ("ADZ"): Andrew Zonenberg
- 8'h00: Antikernel NoC interface
- 8'h01: SPI indirect programming