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[VTA][TSIM] Enable TSIM CI Testing #4407
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@tmoreau89 could you take a look? |
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Thanks Liangfu; did the CI docker image build properly with all of the Chisel dependencies?
@liangfu it seems like there are some errors in the CI; were you able to run the unit tests locally? You may have to test it and run it into the CI docker container. You may want to try it locally on your machine. BTW, the reason I had to comment out these lines of code is because the tests in the docker was causing some issues. I can spend cycles help debug what's wrong. |
It seems to me that Chisel dependencies are handled properly already, except for fixing the @tmoreau89 Yes, I'm able to run the unit tests locally. The error reported in the CI seems to be related to the build configuration. I will put on an update once I found the root cause. |
thanks @liangfu |
Hi @tmoreau89 , I have updated the docker/install/ubuntu_install_chisel.sh, do you have any idea how to reflect the change in the CI pipeline? |
Thanks @liangfu Please send a PR separately for the docker update. Then we can enable tests |
Some recent changes made the unit tests unsuccessful. |
@tmoreau89 As shown in my last commit , all VTA tests are successful with TSIM backend. The latest CI log is reporting failure because we have verilator and sbt installed on docker image v0.55 , but not on v0.52 . |
Thanks for pushing this through to the finish line @liangfu! Can we update the docker image used for CI testing? |
Also do you mind referencing the PR that updates the docker image for future reference? |
Cool, thanks. Since the PRs have been merged, is there a reason why we are still using the old docker image which causes CI to fail? |
I think docker image v0.52 is for i386, and it has no svt and verilator install. Previous docker update v0.55 is for x86-64. |
Oh so you're saying that we cannot run tsim tests on |
Yes, but I'm not quite sure about how to do this. |
I can suggest the following: we can have a |
Sure, let's follow this approach. |
@liangfu great! Can you also update the jenkins file? Please grep for |
@tmoreau89 Jenkinsfile has been revised, but why Jenkins is still evaluating |
hmmm that's odd; try re-triggering it one more time? |
I come to understand the reason now. Although PR #4677 changed the image to v0.55, Jenkins still runs on v0.54 on that PR. Therefore, I think Jenkins is a step late to run everything in Jenkinsfile. For that reason, I've duplicated a copy of task_python_vta_fsim.sh as task_python_vta.sh for now. Once this is merged, we can remove the task_python_vta.sh in a follow up PR, or you might prefer merge #4734 first. |
thank you @liangfu the PR has been merged! |
* Update task_python_vta.sh * install sbt=1.1.1 with apt-get * update verilator_opt * install verilator with major version 4.0 * disable multi-threading for now * bug fix for correcting uop fetch address in LoadUop module * bug fix for correcting uop fetch address in LoadUop module * adjustment to read from dram_offset * enable USE_THREADS with verilator 4.x * DEBUG: try avoid core dump with verilator 4.x * bug fix in LoadUop module * log mega cycles in tsim * download cat.png to avoid fetching in each run * bug fix in LoadUop module * solve dram_even/sram_even issue * bug fix * introduce scalalint in ci * speedup tsim in ci * bug fix * lint scala code before building * disable multi-threading * split fsim/tsim script * update Jenkins settings * duplicate task_python_vta_fsim.sh as task_python_vta.sh for now Co-authored-by: Thierry Moreau <[email protected]>
* Update task_python_vta.sh * install sbt=1.1.1 with apt-get * update verilator_opt * install verilator with major version 4.0 * disable multi-threading for now * bug fix for correcting uop fetch address in LoadUop module * bug fix for correcting uop fetch address in LoadUop module * adjustment to read from dram_offset * enable USE_THREADS with verilator 4.x * DEBUG: try avoid core dump with verilator 4.x * bug fix in LoadUop module * log mega cycles in tsim * download cat.png to avoid fetching in each run * bug fix in LoadUop module * solve dram_even/sram_even issue * bug fix * introduce scalalint in ci * speedup tsim in ci * bug fix * lint scala code before building * disable multi-threading * split fsim/tsim script * update Jenkins settings * duplicate task_python_vta_fsim.sh as task_python_vta.sh for now Co-authored-by: Thierry Moreau <[email protected]>
* Update task_python_vta.sh * install sbt=1.1.1 with apt-get * update verilator_opt * install verilator with major version 4.0 * disable multi-threading for now * bug fix for correcting uop fetch address in LoadUop module * bug fix for correcting uop fetch address in LoadUop module * adjustment to read from dram_offset * enable USE_THREADS with verilator 4.x * DEBUG: try avoid core dump with verilator 4.x * bug fix in LoadUop module * log mega cycles in tsim * download cat.png to avoid fetching in each run * bug fix in LoadUop module * solve dram_even/sram_even issue * bug fix * introduce scalalint in ci * speedup tsim in ci * bug fix * lint scala code before building * disable multi-threading * split fsim/tsim script * update Jenkins settings * duplicate task_python_vta_fsim.sh as task_python_vta.sh for now Co-authored-by: Thierry Moreau <[email protected]>
* Update task_python_vta.sh * install sbt=1.1.1 with apt-get * update verilator_opt * install verilator with major version 4.0 * disable multi-threading for now * bug fix for correcting uop fetch address in LoadUop module * bug fix for correcting uop fetch address in LoadUop module * adjustment to read from dram_offset * enable USE_THREADS with verilator 4.x * DEBUG: try avoid core dump with verilator 4.x * bug fix in LoadUop module * log mega cycles in tsim * download cat.png to avoid fetching in each run * bug fix in LoadUop module * solve dram_even/sram_even issue * bug fix * introduce scalalint in ci * speedup tsim in ci * bug fix * lint scala code before building * disable multi-threading * split fsim/tsim script * update Jenkins settings * duplicate task_python_vta_fsim.sh as task_python_vta.sh for now Co-authored-by: Thierry Moreau <[email protected]>
This PR intends to enable testing Chisel VTA design with the help of TSIM.