update for F1C100s

aodzip · Jul 19, 2020 · 1d0990c · 1d0990c
1 parent 7bb285b
commit 1d0990c
Show file tree

Hide file tree

Showing 4 changed files with 21 additions and 7 deletions.
diff --git a/README.md b/README.md
@@ -90,7 +90,18 @@ ion: ion {
  };
 };
 ```
-### Demo for Allwinner F1C100s / F1C200s (untested)
+### Demo for Allwinner F1C100s / F1C200s
+
+In drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+
+Change
+
+ static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0);
+
+To
+
+ static SUNXI_CCU_GATE(ve_clk, "ve", "pll-ve", 0x13c, BIT(31), 0);
+
 ```
 sram-controller@1c00000 {
  compatible = "allwinner,suniv-f1c100s-system-control",

diff --git a/ion/sunxi/cache.S b/ion/sunxi/cache.S
@@ -1,5 +1,5 @@
 #if __LINUX_ARM_ARCH__ == 7
 #include "cache-v7.S"
 #else
-#warning "[sunxi-cedar] No platform cache flush support"
+#warning "[sunxi-cedar] No BSP asm cache flush support, use dmac flush"
 #endif
diff --git a/ion/sunxi/sunxi_ion.c b/ion/sunxi/sunxi_ion.c
@@ -18,6 +18,7 @@
 #include <linux/of.h>
 #include <linux/mm.h>
 #include <linux/uaccess.h>
+#include <asm/cacheflush.h>
 #include "../ion_priv.h"
 #include "../ion.h"
 #include "../ion_of.h"
@@ -55,21 +56,25 @@ long sunxi_ion_ioctl(struct ion_client *client, unsigned int cmd,
 {
  long ret = 0;
  switch (cmd) {
-#if __LINUX_ARM_ARCH__ == 7
  case ION_IOC_SUNXI_FLUSH_RANGE: {
  sunxi_cache_range range;
  if (copy_from_user(&range, (void __user *)arg,
  sizeof(sunxi_cache_range))) {
  ret = -EINVAL;
  goto end;
  }
+
+#if __LINUX_ARM_ARCH__ == 7
  if (flush_clean_user_range(range.start, range.end)) {
  ret = -EINVAL;
  goto end;
  }
+#else
+ dmac_flush_range((void*)range.start, (void*)range.end);
+#endif
  break;
  }
-
+#if __LINUX_ARM_ARCH__ == 7
  case ION_IOC_SUNXI_FLUSH_ALL: {
  flush_dcache_all();
  break;

diff --git a/ve/cedar_ve.c b/ve/cedar_ve.c
@@ -717,9 +717,6 @@ static long compat_cedardev_ioctl(struct file *filp, unsigned int cmd,
  arg_rate * 1000000)) {
  dev_warn(cedar_devp->platform_dev,
  "set ve clock failed\n");
- } else {
- dev_warn(cedar_devp->platform_dev,
- "set pll4 clock failed\n");
  }
  }
  ret = clk_get_rate(cedar_devp->mod_clk);
@@ -1638,3 +1635,4 @@ MODULE_DESCRIPTION("User mode CEDAR device interface");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(DRV_VERSION);
 MODULE_ALIAS("platform:cedarx-sunxi");
+