Add files via upload

dft/cons/cons.tcl

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+
+# Constraints
+# ----------------------------------------------------------------------------
+#
+# 1. Master Clock Definitions
+#
+# 2. Clock Uncertainties
+#
+# 3. set input/output delay on ports
+#
+# 4. Driving cells
+#
+# 5. Output load
+
+
+####################################################################################
+ #########################################################
+ #### Section 1 : Clock Definition ####
+ #########################################################
+#################################################################################### 
+# 1. Master Clock Definitions 
+# 2. Clock Uncertainties
+# 3. Clock Transitions
+####################################################################################
+
+#baud rate =115200 bits/sec = 112.5 KHz
+
+# UART_CLK_TX = 112.5 KHz
+set CLK1_NAME UART_CLK_TX
+set CLK1_PER 8680.5
+
+# UART_CLK_RX =115200 * 32= 3.515 MHz
+set CLK2_NAME UART_CLK_RX
+set CLK2_PER 271.316
+
+#SCAN_CLK (10 MHZ)
+set CLK3_NAME SCAN_CLK
+set CLK3_PER 100
+
+set CLK_SETUP_SKEW 0.25
+set CLK_HOLD_SKEW 0.1
+set CLK_TRA 0.1
+
+
+create_clock -name $CLK1_NAME -period $CLK1_PER -waveform "0 [expr $CLK1_PER/2]" [get_ports TX_CLK]
+set_clock_uncertainty -setup $CLK_SETUP_SKEW [get_clocks $CLK1_NAME]
+set_clock_uncertainty -hold $CLK_HOLD_SKEW [get_clocks $CLK1_NAME]
+
+create_clock -name $CLK2_NAME -period $CLK2_PER -waveform "0 [expr $CLK2_PER/2]" [get_ports RX_CLK]
+set_clock_uncertainty -setup $CLK_SETUP_SKEW [get_clocks $CLK2_NAME]
+set_clock_uncertainty -hold $CLK_HOLD_SKEW [get_clocks $CLK2_NAME]
+
+# Scan clocks
+create_clock -name $CLK3_NAME -period $CLK3_PER -waveform "0 [expr $CLK3_PER/2]" [get_ports scan_clk]
+set_clock_uncertainty -setup $CLK_SETUP_SKEW [get_clocks $CLK3_NAME]
+set_clock_uncertainty -hold $CLK_HOLD_SKEW [get_clocks $CLK3_NAME]
+
+set_clock_transition -rise $CLK_TRA [get_clocks $CLK1_NAME] 
+set_clock_transition -rise $CLK_TRA [get_clocks $CLK2_NAME] 
+
+# Don’t optimize logic crossing clock domains
+set_false_path -from [get_clocks $CLK1_NAME] -to [get_clocks $CLK2_NAME]
+set_false_path -from [get_clocks $CLK2_NAME] -to [get_clocks $CLK1_NAME]
+
+####################################################################################
+ #########################################################
+ #### Section 2 : Clocks Relationship ####
+ #########################################################
+####################################################################################
+
+set_clock_groups -asynchronous -group [get_clocks {UART_CLK_TX UART_CLK_RX}] \
+ -group [get_clocks SCAN_CLK] 
+####################################################################################
+ #########################################################
+ #### Section 2 : set input/output delay on ports ####
+ #########################################################
+####################################################################################
+
+set in_delay [expr 0.3*$CLK2_PER]
+set out_delay [expr 0.3*$CLK2_PER]
+
+#Constrain Input Paths
+set_input_delay $in_delay -clock $CLK2_NAME [remove_from_collection [all_inputs] [get_ports {scan_clk TX_CLK RX_CLK RST}]]
+
+
+#Constrain Output Paths
+set_output_delay $out_delay -clock $CLK2_NAME [all_outputs]
+
+####################################################################################
+ #########################################################
+ #### Section 4 : Driving cells ####
+ #########################################################
+####################################################################################
+
+set_driving_cell -no_design_rule -max -lib_cell NBUFFX4_RVT [remove_from_collection [all_inputs] [get_ports {scan_clk TX_CLK RX_CLK}]]
+
+####################################################################################
+ #########################################################
+ #### Section 5 : Output load ####
+ #########################################################
+####################################################################################
+
+set_load -max [expr {2 * [load_of saed32rvt_ss0p75v125c/NBUFFX4_RVT/A]}] [all_outputs]
+
+####################################################################################
+ #########################################################
+ #### Section 6 : min and max library ####
+ #########################################################
+####################################################################################
+
+set_min_library saed32rvt_ss0p75v125c.db -min_version saed32rvt_ff1p16vn40c.db
+
+####################################################################################
+ #########################################################
+ #### Section 7 : wireload Model ####
+ #########################################################
+####################################################################################
+
+set auto_wire_load_selection area_reselect
+set_wire_load_mode enclosed
+set_wire_load_selection_group predcaps
+
+####################################################################################
+ #########################################################
+ #### Section 8 : set_case_analysis ####
+ #########################################################
+####################################################################################
+
+set_case_analysis 1 [get_port test_mode]

dft/output/UART.def

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+VERSION 5.5 ;
+NAMESCASESENSITIVE ON ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN UART ;
+
+SCANCHAINS 1 ;
+
+- 1
++ START PIN SI
++ FLOATING U0_UART_RX/U0_data_sampling/Samples_reg_0_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_data_sampling/Samples_reg_1_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_data_sampling/Samples_reg_2_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_data_sampling/sampled_bit_reg ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_deserializer/P_DATA_reg_0_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_deserializer/P_DATA_reg_1_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_deserializer/P_DATA_reg_2_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_deserializer/P_DATA_reg_3_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_deserializer/P_DATA_reg_4_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_deserializer/P_DATA_reg_5_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_deserializer/P_DATA_reg_6_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_deserializer/P_DATA_reg_7_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_par_chk/par_err_reg ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_stp_chk/stp_err_reg ( IN SI ) ( OUT Q )
+ U0_UART_RX/U0_strt_chk/strt_glitch_reg ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_uart_fsm/current_state_reg_0_ ( IN SI ) ( OUT Q )
+ U0_UART_RX/U0_uart_fsm/current_state_reg_1_ ( IN SI ) ( OUT QN )
+ U0_UART_RX/U0_uart_fsm/current_state_reg_2_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_Serializer/DATA_V_reg_0_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_Serializer/DATA_V_reg_1_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_Serializer/DATA_V_reg_2_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_Serializer/DATA_V_reg_3_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_Serializer/DATA_V_reg_4_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_Serializer/DATA_V_reg_5_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_Serializer/DATA_V_reg_6_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_Serializer/DATA_V_reg_7_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_Serializer/ser_count_reg_0_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_Serializer/ser_count_reg_1_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_Serializer/ser_count_reg_2_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_fsm/busy_reg ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_fsm/current_state_reg_0_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_fsm/current_state_reg_1_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_fsm/current_state_reg_2_ ( IN SI ) ( OUT Q )
+ U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ ( IN SI ) ( OUT Q )
+ U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ ( IN SI ) ( OUT Q )
+ U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ ( IN SI ) ( OUT Q )
+ U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ ( IN SI ) ( OUT Q )
+ U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ ( IN SI ) ( OUT Q )
+ U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ ( IN SI ) ( OUT Q )
+ U0_UART_TX/U0_parity_calc/parity_reg ( IN SI ) ( OUT QN )
+ U0_UART_TX/U0_mux/OUT_reg ( IN SI ) ( OUT Q )
++ PARTITION scan_clk_30_30
++ STOP PIN SO ;
+
+END SCANCHAINS
+
+END DESIGN

dft/output/UART_mapped.sdc

@@ -0,0 +1,103 @@
+###################################################################
+
+# Created by write_sdc on Thu Apr 18 17:18:50 2024
+
+###################################################################
+set sdc_version 2.1
+
+set_units -time ns -resistance MOhm -capacitance fF -voltage V -current uA
+set_wire_load_mode enclosed
+set_wire_load_selection_group predcaps
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports RST]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports RX_IN_S]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[7]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[6]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[5]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[4]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[3]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[2]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[1]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {TX_IN_P[0]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports TX_IN_V]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[5]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[4]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[3]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[2]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[1]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports {Prescale[0]}]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports parity_enable]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports parity_type]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports SI]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports SE]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports scan_rst]
+set_driving_cell -max -lib_cell NBUFFX4_RVT -no_design_rule [get_ports test_mode]
+set_load -pin_load 1.18475 [get_ports {RX_OUT_P[7]}]
+set_load -pin_load 1.18475 [get_ports {RX_OUT_P[6]}]
+set_load -pin_load 1.18475 [get_ports {RX_OUT_P[5]}]
+set_load -pin_load 1.18475 [get_ports {RX_OUT_P[4]}]
+set_load -pin_load 1.18475 [get_ports {RX_OUT_P[3]}]
+set_load -pin_load 1.18475 [get_ports {RX_OUT_P[2]}]
+set_load -pin_load 1.18475 [get_ports {RX_OUT_P[1]}]
+set_load -pin_load 1.18475 [get_ports {RX_OUT_P[0]}]
+set_load -pin_load 1.18475 [get_ports RX_OUT_V]
+set_load -pin_load 1.18475 [get_ports TX_OUT_S]
+set_load -pin_load 1.18475 [get_ports TX_OUT_V]
+set_load -pin_load 1.18475 [get_ports parity_error]
+set_load -pin_load 1.18475 [get_ports framing_error]
+set_load -pin_load 1.18475 [get_ports SO]
+set_case_analysis 1 [get_ports test_mode]
+create_clock [get_ports TX_CLK] -name UART_CLK_TX -period 8680.5 -waveform {0 4340.25}
+set_clock_uncertainty -setup 0.25 [get_clocks UART_CLK_TX]
+set_clock_uncertainty -hold 0.1 [get_clocks UART_CLK_TX]
+set_clock_transition -min -rise 0.1 [get_clocks UART_CLK_TX]
+set_clock_transition -max -rise 0.1 [get_clocks UART_CLK_TX]
+create_clock [get_ports RX_CLK] -name UART_CLK_RX -period 271.316 -waveform {0 135.658}
+set_clock_uncertainty -setup 0.25 [get_clocks UART_CLK_RX]
+set_clock_uncertainty -hold 0.1 [get_clocks UART_CLK_RX]
+set_clock_transition -min -rise 0.1 [get_clocks UART_CLK_RX]
+set_clock_transition -max -rise 0.1 [get_clocks UART_CLK_RX]
+create_clock [get_ports scan_clk] -name SCAN_CLK -period 100 -waveform {0 50}
+set_clock_uncertainty -setup 0.25 [get_clocks SCAN_CLK]
+set_clock_uncertainty -hold 0.1 [get_clocks SCAN_CLK]
+group_path -name INOUT -from [list [get_ports RST] [get_ports TX_CLK] [get_ports RX_CLK] [get_ports RX_IN_S] [get_ports {TX_IN_P[7]}] [get_ports {TX_IN_P[6]}] [get_ports {TX_IN_P[5]}] [get_ports {TX_IN_P[4]}] [get_ports {TX_IN_P[3]}] [get_ports {TX_IN_P[2]}] [get_ports {TX_IN_P[1]}] [get_ports {TX_IN_P[0]}] [get_ports TX_IN_V] [get_ports {Prescale[5]}] [get_ports {Prescale[4]}] [get_ports {Prescale[3]}] [get_ports {Prescale[2]}] [get_ports {Prescale[1]}] [get_ports {Prescale[0]}] [get_ports parity_enable] [get_ports parity_type] [get_ports SI] [get_ports SE] [get_ports scan_clk] [get_ports scan_rst] [get_ports test_mode]] -to [list [get_ports {RX_OUT_P[7]}] [get_ports {RX_OUT_P[6]}] [get_ports {RX_OUT_P[5]}] [get_ports {RX_OUT_P[4]}] [get_ports {RX_OUT_P[3]}] [get_ports {RX_OUT_P[2]}] [get_ports {RX_OUT_P[1]}] [get_ports {RX_OUT_P[0]}] [get_ports RX_OUT_V] [get_ports TX_OUT_S] [get_ports TX_OUT_V] [get_ports parity_error] [get_ports framing_error] [get_ports SO]]
+group_path -name INREG -from [list [get_ports RST] [get_ports TX_CLK] [get_ports RX_CLK] [get_ports RX_IN_S] [get_ports {TX_IN_P[7]}] [get_ports {TX_IN_P[6]}] [get_ports {TX_IN_P[5]}] [get_ports {TX_IN_P[4]}] [get_ports {TX_IN_P[3]}] [get_ports {TX_IN_P[2]}] [get_ports {TX_IN_P[1]}] [get_ports {TX_IN_P[0]}] [get_ports TX_IN_V] [get_ports {Prescale[5]}] [get_ports {Prescale[4]}] [get_ports {Prescale[3]}] [get_ports {Prescale[2]}] [get_ports {Prescale[1]}] [get_ports {Prescale[0]}] [get_ports parity_enable] [get_ports parity_type] [get_ports SI] [get_ports SE] [get_ports scan_clk] [get_ports scan_rst] [get_ports test_mode]]
+group_path -name REGOUT -to [list [get_ports {RX_OUT_P[7]}] [get_ports {RX_OUT_P[6]}] [get_ports {RX_OUT_P[5]}] [get_ports {RX_OUT_P[4]}] [get_ports {RX_OUT_P[3]}] [get_ports {RX_OUT_P[2]}] [get_ports {RX_OUT_P[1]}] [get_ports {RX_OUT_P[0]}] [get_ports RX_OUT_V] [get_ports TX_OUT_S] [get_ports TX_OUT_V] [get_ports parity_error] [get_ports framing_error] [get_ports SO]]
+set_false_path -from [get_clocks UART_CLK_TX] -to [get_clocks UART_CLK_RX]
+set_false_path -from [get_clocks UART_CLK_RX] -to [get_clocks UART_CLK_TX]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports RX_IN_S]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[7]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[6]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[5]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[4]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[3]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[2]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[1]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {TX_IN_P[0]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports TX_IN_V]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[5]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[4]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[3]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[2]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[1]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports {Prescale[0]}]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports parity_enable]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports parity_type]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports SI]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports SE]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports scan_rst]
+set_input_delay -clock UART_CLK_RX 81.3948 [get_ports test_mode]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[7]}]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[6]}]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[5]}]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[4]}]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[3]}]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[2]}]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[1]}]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports {RX_OUT_P[0]}]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports RX_OUT_V]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports TX_OUT_S]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports TX_OUT_V]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports parity_error]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports framing_error]
+set_output_delay -clock UART_CLK_RX 81.3948 [get_ports SO]
+set_clock_groups -asynchronous -name UART_CLK_TX_1 -group [list [get_clocks UART_CLK_TX] [get_clocks UART_CLK_RX]] -group [get_clocks SCAN_CLK]