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Update README.md
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basemhesham committed Apr 29, 2024
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Expand Up @@ -39,8 +39,10 @@ UART_CLK_RX =115200 * 32 = 3.515 MHz
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## Simulation using VCS
### UART_RX simulation
![Test7](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/58055bd7-a6f3-4ce0-8e29-c399697ca906)
<br> <br>
### UART_TX simulation
![Test2](https://github.com/basemhesham/Design-and-ASIC-Implementation-of-UART/assets/136960296/807dc089-16ea-4de2-90c2-414951b9ce5a)

## Synthesized View of UART chip (post DFT)
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