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1. signalflip-js signalflip-js Public

   verilator testbench w/ Javascript using N-API

   C++ 18 3

2. basic-signalflip-example basic-signalflip-example Public

   Signalflip example: simulate counter rtl

   Makefile 2

3. leading-zeroes-counter leading-zeroes-counter Public

   Leading zeroes counter (SystemVerilog)

   Makefile 3

4. reciprocal-sv reciprocal-sv Public

   Fixed point reciprocal in SystemVerilog

   Makefile 4

5. APB3-config-regs APB3-config-regs Public

   Implements two config registers with APB3 interface. Verification testbench done in verilator using signalflip-js

   C++ 1

6. elastic-buffer elastic-buffer Public

   buffers for valid-ready designs

   SystemVerilog 3