Learning how to make a RISC-V

An open-source static random access memory (SRAM) compiler.

RISC-V Instruction Set Manual

A FPGA friendly 32 bit RISC-V CPU implementation

Amphion (/æmˈfaɪən/) is a toolkit for Audio, Music, and Speech Generation. Its purpose is to support reproducible research and help junior researchers and engineers get started in the field of audi…

HIP: C++ Heterogeneous-Compute Interface for Portability

oneAPI Math Kernel Library (oneMKL) Interfaces

OpenBLAS is an optimized BLAS library based on GotoBLAS2 1.13 BSD version.

building ROS in 500 lines of Go

Open-Sora: Democratizing Efficient Video Production for All

A machine learning-based lossless video super resolution framework. Est. Hack the Valley II, 2018.

A blazing fast, information dense media player built with Next.js.

FPGA project to man-in-the-middle attack Flexray

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

6502 FPGA implementation

Interactive Repl Over Neovim

A neovim plugin to navigate and execute code cells

Interact with Jupyter from NeoVim.

A clock-accurate FPGA clone of the NMOs processor 6502, created on the basis of reverse engineering.

A clock-accurate FPGA clone of the NMOs processor 6502, created on the basis of reverse engineering.

An implementation of the Z80 CPU for Altera, Xilinx and Lattice FPGAs

Simple system package management tool for Go

RISC-V CPU Core (RV32IM)

A very compact representation of a placeholder for an image.

A toy implementation of monocular SLAM written while livestreaming

Implementations from the free course Deep Reinforcement Learning with Tensorflow and PyTorch

🔥🕷️ Crawl4AI: Open-source LLM Friendly Web Crawler & Scrapper

a simple unofficial implementation of classifier-free diffusion guidance