Merge branch 'solutions'

ProblemSets/PDS-ProblemSet-02/solution/problem_2_1.vhd

@@ -0,0 +1,45 @@
+--/*
+--**********************************************************
+-- Design Automation Course Homework (Spring, 2020 Semester)
+-- Amirkabir University of Technology (Tehran Polytechnic)
+-- Department of Computer Engineering (CE-AUT)
+-- https://ce.aut.ac.ir
+-- Designed TA (ali[dot]mohammadpour[at]ac[dot]ir)
+-- *******************************************************
+-- Student ID : XXXXXXX
+-- Student Name: -----------------
+-- Student Mail: -----------------
+-- *******************************************************
+-- Module: ProblemSet 2, Problem 1
+-- *******************************************************
+-- Additional Comments:
+--*/
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package problem_2_1 is
+
+ subtype ip_t is std_logic_vector(31 downto 0) ;
+ subtype port_t is std_logic_vector(15 downto 0);
+ subtype mac_addr_t is std_logic_vector(47 downto 0);
+ subtype service_t is std_logic_vector(15 downto 0);
+
+ type mac_udp_ip_stack_t is record
+ src_ip : ip_t;
+ dst_ip : ip_t;
+ src_port : port_t;
+ dst_port : port_t;
+ mac_addr: mac_addr_t;
+ seq_num : service_t;
+ ack_num : service_t;
+ qos_num : service_t;
+ end record;
+
+end package problem_2_1;
+
+package body problem_2_1 is
+
+ -- write codes here 
+
+end package body problem_2_1;

ProblemSets/PDS-ProblemSet-02/solution/problem_2_2.vhd

@@ -0,0 +1,170 @@
+--/*
+--**********************************************************
+-- Design Automation Course Homework (Spring, 2020 Semester)
+-- Amirkabir University of Technology (Tehran Polytechnic)
+-- Department of Computer Engineering (CE-AUT)
+-- https://ce.aut.ac.ir
+-- Designed TA (ali[dot]mohammadpour[at]ac[dot]ir)
+-- *******************************************************
+-- Student ID : TA
+-- Student Name: TA
+-- Student Mail: TA
+-- *******************************************************
+-- Module: ProblemSet 2, Problem 2
+-- *******************************************************
+-- Additional Comments:
+--*/
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_signed.all;
+
+entity problem_2_2 is
+ port (
+ a : in std_logic_vector(7 downto 0) ;
+ b : in std_logic_vector(7 downto 0) ;
+ c : in std_logic_vector(7 downto 0) ;
+ d : in std_logic_vector(7 downto 0) ;
+
+ mode : in std_logic;
+
+ y0 : out std_logic_vector(7 downto 0) ;
+ y1 : out std_logic_vector(7 downto 0) ;
+ y2 : out std_logic_vector(7 downto 0) ;
+ y3 : out std_logic_vector(7 downto 0)) ;
+
+end problem_2_2;
+
+architecture problem_2_2_arc of problem_2_2 is
+
+ component crossbar is
+ port (
+ inp_1 : in std_logic_vector(7 downto 0) ;
+ inp_2 : in std_logic_vector(7 downto 0) ;
+ mode : in std_logic ;
+ out_1 : out std_logic_vector(7 downto 0) ;
+ out_2 : out std_logic_vector(7 downto 0)) ;
+ end component ; -- crossbar
+
+ signal w10, w11, w12, w13,
+ w21, w22, w31, w32
+ : std_logic_vector(7 downto 0) ;
+
+begin
+
+ -- instances of level 1 (up module)
+ cb_11 : crossbar
+ port map (
+ inp_1 => a,
+ inp_2 => b,
+ mode => mode,
+ out_1 => w10,
+ out_2 => w11
+ );
+
+ cb_12 : crossbar
+ port map (
+ inp_1 => c,
+ inp_2 => d,
+ mode => mode,
+ out_1 => w12,
+ out_2 => w13
+ );
+
+ -- instances of level 2
+ cb_2 : crossbar
+ port map (
+ inp_1 => w11,
+ inp_2 => w12,
+ mode => mode,
+ out_1 => w21,
+ out_2 => w22
+ );
+ -- instances of level 3
+ cb_31 : crossbar
+ port map (
+ inp_1 => w10,
+ inp_2 => w21,
+ mode => mode,
+ out_1 => y0,
+ out_2 => w31
+ );
+
+ cb_32 : crossbar
+ port map (
+ inp_1 => w22,
+ inp_2 => w13,
+ mode => mode,
+ out_1 => w32,
+ out_2 => y3
+ );
+
+ -- instances of level 4
+ cb_4 : crossbar
+ port map (
+ inp_1 => w31,
+ inp_2 => w32,
+ mode => mode,
+ out_1 => y1,
+ out_2 => y2
+ );
+
+end problem_2_2_arc;
+
+------------------------------------------------
+------- describe new modules here --------------
+------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_signed.all;
+
+entity crossbar is
+ port (
+ inp_1 : in std_logic_vector(7 downto 0) ;
+ inp_2 : in std_logic_vector(7 downto 0) ;
+ mode : in std_logic;
+ out_1 : out std_logic_vector(7 downto 0) ;
+ out_2 : out std_logic_vector(7 downto 0)) ;
+
+end entity ; -- crossbar
+
+architecture behavioral of crossbar is
+
+begin
+
+ arch_proc : process( inp_1, inp_2, mode)
+
+ begin
+
+
+ if (mode = '0') then
+ if ((to_integer(signed(inp_2)) < to_integer(signed(inp_1)))) then
+
+ out_1 <= inp_1 ;
+ out_2 <= inp_2 ;
+
+ else
+
+ out_1 <= inp_2 ;
+ out_2 <= inp_1 ;
+
+ end if;
+ else
+ if ((to_integer(signed(inp_2)) < to_integer(signed(inp_1)))) then
+
+ out_1 <= inp_2 ;
+ out_2 <= inp_1 ;
+
+ else
+
+ out_1 <= inp_1 ;
+ out_2 <= inp_2 ;
+
+ end if;
+
+ end if;
+ end process ; -- arch_proc
+
+end architecture ; -- behavioral

ProblemSets/PDS-ProblemSet-02/solution/problem_2_3_a.vhd

@@ -0,0 +1,46 @@
+--/*
+--**********************************************************
+-- Design Automation Course Homework (Spring, 2020 Semester)
+-- Amirkabir University of Technology (Tehran Polytechnic)
+-- Department of Computer Engineering (CE-AUT)
+-- https://ce.aut.ac.ir
+-- Designed TA (ali[dot]mohammadpour[at]ac[dot]ir)
+-- *******************************************************
+-- Student ID : XXXXXXX
+-- Student Name: -----------------
+-- Student Mail: -----------------
+-- *******************************************************
+-- Module: ProblemSet 2, Problem 3, Section B
+-- *******************************************************
+-- Additional Comments:
+--*/
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+
+entity problem_2_3_a is
+ port (
+ data_inp : in std_logic_vector(7 downto 0) ;
+ shamt : in std_logic_vector(2 downto 0) ;
+ shmod : in std_logic ; 
+ data_out : out std_logic_vector(7 downto 0));
+
+end problem_2_3_a;
+
+architecture problem_2_3_a_arc of problem_2_3_a is
+
+begin
+ data_out <= 
+ std_logic_vector(shift_right(unsigned(data_inp), to_integer(unsigned(shamt)))) when shmod = '1' else
+ std_logic_vector(shift_right(signed(data_inp), to_integer(unsigned(shamt))));
+
+ -- Note : Functions 'SRA' and 'SRL' is not compatible with VHDL 1076-1987. 
+ -- Comment out the function (declaration and body) for VHDL 1076-1987 compatibility.
+
+ -- dataout <= data_inp srl to_integer(unsigned(data_inp)) when shmod = '1' else
+ -- data_inp sra to_integer(unsigned(data_inp))
+
+end problem_2_3_a_arc;

ProblemSets/PDS-ProblemSet-02/solution/problem_2_3_b.vhd

@@ -0,0 +1,63 @@
+--/*
+--**********************************************************
+-- Design Automation Course Homework (Spring, 2020 Semester)
+-- Amirkabir University of Technology (Tehran Polytechnic)
+-- Department of Computer Engineering (CE-AUT)
+-- https://ce.aut.ac.ir
+-- Designed TA (ali[dot]mohammadpour[at]ac[dot]ir)
+-- *******************************************************
+-- Student ID : XXXXXXX
+-- Student Name: -----------------
+-- Student Mail: -----------------
+-- *******************************************************
+-- Module: ProblemSet 2, Problem 3, Section B
+-- *******************************************************
+-- Additional Comments:
+--*/
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity problem_2_3_b is
+ port (
+ data_inp : in std_logic_vector(7 downto 0) ;
+ shamt : in std_logic_vector(2 downto 0) ;
+ shmod : in std_logic ; 
+ data_out : out std_logic_vector(7 downto 0));
+
+end problem_2_3_b;
+
+architecture problem_2_3_b_arc of problem_2_3_b is
+
+function right_shifter (
+ data : std_logic_vector;
+ shamt : std_logic_vector;
+ shmod : std_logic)
+ return std_logic_vector is
+ variable result : std_logic_vector(data'range);
+begin
+ lbl : for i in 0 to shamt'length loop
+ if (i + shamt < data'length) then
+ result(i) := data(i+ to_integer(unsigned(shamt))) ;
+ end if;
+ end loop;
+
+ sign : for i in to_integer(unsigned(shamt)) to result'length loop
+ if (shmod = '0') then
+ result(i) := '0' ;
+ else
+ result(i) := data(data'length-1) ;
+ end if;
+ end loop;
+
+ return result;
+
+end function right_shifter;
+
+begin
+
+ data_out <= right_shifter(data_inp, shamt, shmod);
+
+end problem_2_3_b_arc;