fix: Ports Vector Size Problem-53

aliemo · May 26, 2020 · 76800fc · 76800fc
1 parent 4aadeeb
commit 76800fc
Showing 1 changed file with 6 additions and 6 deletions.
diff --git a/ProblemSets/PDS-ProblemSet-05/src/Problem53/tb_sine_cosine_module.vhd b/ProblemSets/PDS-ProblemSet-05/src/Problem53/tb_sine_cosine_module.vhd
@@ -34,21 +34,21 @@ architecture testbench of tb_sine_cosine_module is
  port (
  aclk : in std_logic ;
  din_tvalid : in std_logic ;
- din : in std_logic_vector(16 downto 0) ;
+ din : in std_logic_vector(15 downto 0) ;
  din_tready : out std_logic ;
  dout_tvalid : out std_logic ;
- dout_sine : out std_logic_vector(16 downto 0);
- dout_cosine : out std_logic_vector(16 downto 0)
+ dout_sine : out std_logic_vector(15 downto 0);
+ dout_cosine : out std_logic_vector(15 downto 0)
  ) ;
  end component sine_cosine_module;
 
  signal aclk : std_logic ;
  signal din_tvalid : std_logic ;
- signal din : std_logic_vector(16 downto 0) ;
+ signal din : std_logic_vector(15 downto 0) ;
  signal din_tready : std_logic ;
  signal dout_tvalid : std_logic ;
- signal dout_sine : std_logic_vector(16 downto 0);
- signal dout_cosine : std_logic_vector(16 downto 0)
+ signal dout_sine : std_logic_vector(15 downto 0);
+ signal dout_cosine : std_logic_vector(15 downto 0)
 
 begin