An ATE Pattern Generator for PULP chips and JTAG Taps in general

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

Tag bus transactions by target address

Build GNU/Linux for various PULP/Cheshire-based systems.

A Plug-and-play Lightweight tool for the Inference Optimization of Deep Neural networks

A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.

A reliable, real-time subsystem for the Carfield SoC

My emacs dotfile, inspired by spacemacs.

A Fast, Low-Overhead On-chip Network

A high-efficiency system-on-chip for floating-point compute workloads.

RISC-V fast interrupt controller

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

Linux kernel source tree

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

A highly scalable framework for the performance and energy monitoring of HPC servers

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

⛔ DEPRECATED ⛔ Lean but mean RISC-V system!

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software …

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.