Hey There! Welcome to my journey of dissecting and exploring the corners of Transaction Level Verilog HDL! 100 days of building and experimenting! Together, we will look to upskill and learn more about the features and barriers this language helps in breaking while building hardware relevant to a designer.
This entire exercise is carried out in Makerchip IDE courtesy of Redwood EDA.
| Day | Makerchip IDE | Content Elaboration |
|---|---|---|
| 1 | CombinatorialLogicRundown.tlv | Day1.md |
| 2 | CombinatorialLogicExtended.tlv | Day2.md |
| 3 | SequentialScope.tlv | Day3.md |
| 4 | FibonacciPlayground.tlv | Day4.md |
| 5 | PythagoreanFlex.tlv | Day5.md |
| 6 | HierarchicalIncrementer.tlv | Day6.md |
| 7 | RippleCarryAdder.tlv | Day7.md |
| 8 | FPGAMultiplier.tlv | Day8.md |
| 9 | LongDivision.tlv | Day9.md |
| 10 | 32bitALU.tlv | Day10.md |