LLM101n: Let's build a Storyteller

Mirror your github repositories to your gitea server

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

A list of Free Software network services and web applications which can be hosted on your own servers

Stable Diffusion web UI

Lord of Large Language Models Web User Interface

A Gradio web UI for Large Language Models.

YosysHQ SVA AXI Properties

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

64-bit multicore RISC-V processor

Simple program to read & write to a pci device from userspace

Xlinix Kintex 7 based PCIE development board

Infrastructure to enable deployment of ML models to low-power resource-constrained embedded targets (including microcontrollers and digital signal processors).

It contains a curated list of awesome RISC-V Resources.

Caliptra IP and firmware for integrated Root of Trust block

Envision a future where every student can read all the code of a teaching operating system.

RSD: RISC-V Out-of-Order Superscalar Processor

A List of Free and Open Source Hardware Verification Tools and Frameworks

SystemVerilog parser library fully compliant with IEEE 1800-2017

A Zsh theme

lowRISC Style Guides

Dear ImGui Bundle: an extensive set of Ready-to-use widgets and libraries, based on ImGui. Start your first app in 5 lines of code, or less. Whether you prefer Python or C++, this pack has your back!

Chisel examples and code snippets

Chisel HDL Template Repository

Latex templates for documents of INF/UFRGS

Xilinx Embedded Software (embeddedsw) Development

Send video/audio over HDMI on an FPGA

An AXI4 crossbar implementation in SystemVerilog

C header file writer plugin for RgGen