100x RISC-V cores MPSoC

Please read this to understand the design.

To build the design and run sims with Verilator:

make all

To open waves with gtkwave:

make wave

To build for Xilinx FPGA Kintex 7:

make fpga

Name		Name	Last commit message	Last commit date
Latest commit History 30 Commits
.vscode		.vscode
altera		altera
rtl		rtl
sw		sw
tb		tb
xilinx		xilinx
.editorconfig		.editorconfig
.gitignore		.gitignore
.gitmodules		.gitmodules
README.md		README.md
config.vlt		config.vlt
example_mpsoc.core		example_mpsoc.core
example_mpsoc_1.0.0_0.bit		example_mpsoc_1.0.0_0.bit
makefile		makefile
mpsoc_100xfinal_report_synth.rpt		mpsoc_100xfinal_report_synth.rpt
mpsoc_10x10		mpsoc_10x10
mpsoc_4x4		mpsoc_4x4
tags		tags
tmpl.gtkw		tmpl.gtkw
verilator.flags		verilator.flags

Provide feedback