Stars
IronMan+alpha: Graph Neural Network and Reinforcement Learning in High-Level Synthesis
Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"
TinyTapeout submission with the SN76489 Digital Complex Sound Generator (DCSG) programmable sound generator (PSG) chip from Texas Instruments.
The source for the Linux kernel used in Windows Subsystem for Linux 2 (WSL2)
Project F brings FPGAs to life with exciting open-source designs you can build on.
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
Verilog demo for Tiny Tapeout 03
FEMU: Accurate, Scalable and Extensible NVMe SSD Emulator (FAST'18)
Digital Logical Designs Course Projects
Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Square Root Operations based on the IEEE-754 standard for float…
Verilog implementation of multi-stage 32-bit RISC-V processor
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
120+ Common code and interview problems solved in Python **(it's GROWING...)** Give a Star 🌟If it helps you. Please go through the README.md before starting.
HydraBus HydraFW official firmware for open source multi-tool for anyone interested in learning/developping/debugging/hacking/Penetration Testing for basic or advanced embedded hardware
GNU toolchain for RISC-V, including GCC
FPGA Design of a Neural Network for Color Detection
A C++ version of jMetal, a Java framework aimed at multi-objective optimization with metaheuristics.