Skip to content
View ad-astra-et-ultra's full-sized avatar
  • National Institute of Technology Durgapur
  • West Bengal, India

Block or report ad-astra-et-ultra

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Beta Lists are currently in beta. Share feedback and report bugs.
Showing results

A collection of full time roles in SWE, Quant, and PM for new grads.

10,879 1,022 Updated Sep 2, 2024

Documenting the Xilinx 7-series bit-stream format.

Python 753 148 Updated Aug 31, 2024

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

SystemVerilog 163 50 Updated Jan 18, 2024

A modular build system for hardware

Python 818 83 Updated Sep 2, 2024

Detecting and Tracking cars from a video using YOLOv8 model and object tracking framework (abewley/sort)

Python 12 2 Updated Mar 4, 2023

GeAr low latency adder implementation and error analysis

Verilog 4 1 Updated Feb 12, 2023

Cyclofit tracks the heart rate,calories burnt, distance coverered and much more using the sensors integrated in a single device.Our device has a proximity sensor that can track any incoming vehicle…

Kotlin 25 8 Updated Dec 28, 2023

The Score Specification provides a developer-centric and platform-agnostic Workload specification to improve developer productivity and experience. It eliminates configuration inconsistencies betwe…

Makefile 7,767 2,210 Updated Aug 8, 2024

A single cycle MIPS RISC-V CPU Core using Verilog

Verilog 5 1 Updated Feb 12, 2023