EECS Ph.D. Student at ADEPT Lab
-
University of California at Berkeley
- Berkeley, California
- abejgonzalez.github.io
Block or Report
Block or report abejgonzalez
Report abuse
Contact GitHub support about this user’s behavior. Learn more about reporting abuse.
Report abusePinned Loading
-
ucb-bar/chipyard
ucb-bar/chipyard PublicAn Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
-
firesim
firesim PublicForked from firesim/firesim
FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation of RISC-V Systems (Rocket Chip, BOOM) in the Cloud
Python 1
-
firechip
firechip PublicForked from firesim/firechip
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
C
-
-
coremarkpro-util-make-riscv
coremarkpro-util-make-riscv PublicForked from ccelio/coremarkpro-util-make-riscv
The utility files to port CoreMark-Pro to RISC-V.
Makefile
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.