Add asm! support for mips64

abao168899 · Oct 4, 2020 · 79f477b · 79f477b
1 parent 6cb062d
commit 79f477b
Show file tree

Hide file tree

Showing 5 changed files with 118 additions and 82 deletions.
diff --git a/compiler/rustc_codegen_llvm/src/asm.rs b/compiler/rustc_codegen_llvm/src/asm.rs
@@ -259,7 +259,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
  InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
  InlineAsmArch::Nvptx64 => {}
  InlineAsmArch::Hexagon => {}
- InlineAsmArch::Mips => {}
+ InlineAsmArch::Mips | InlineAsmArch::Mips64 => {}
  }
  }
  if !options.contains(InlineAsmOptions::NOMEM) {
@@ -710,6 +710,7 @@ fn llvm_fixup_input(
  // MIPS only supports register-length arithmetics.
  Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
  Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
+ Primitive::F64 => bx.bitcast(value, bx.cx.type_i64()),
  _ => value,
  },
  _ => value,
@@ -785,6 +786,7 @@ fn llvm_fixup_output(
  Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
  Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
  Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
+ Primitive::F64 => bx.bitcast(value, bx.cx.type_f64()),
  _ => value,
  },
  _ => value,
@@ -854,6 +856,7 @@ fn llvm_fixup_output_type(
  // MIPS only supports register-length arithmetics.
  Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
  Primitive::F32 => cx.type_i32(),
+ Primitive::F64 => cx.type_i64(),
  _ => layout.llvm_type(cx),
  },
  _ => layout.llvm_type(cx),

diff --git a/compiler/rustc_target/src/asm/mips.rs b/compiler/rustc_target/src/asm/mips.rs
@@ -32,11 +32,12 @@ impl MipsInlineAsmRegClass {
 
  pub fn supported_types(
  self,
- _arch: InlineAsmArch,
+ arch: InlineAsmArch,
  ) -> &'static [(InlineAsmType, Option<&'static str>)] {
- match self {
- Self::reg => types! { _: I8, I16, I32, F32; },
- Self::freg => types! { _: F32, F64; },
+ match (self, arch) {
+ (Self::reg, InlineAsmArch::Mips64) => types! { _: I8, I16, I32, I64, F32, F64; },
+ (Self::reg, _) => types! { _: I8, I16, I32, F32; },
+ (Self::freg, _) => types! { _: F32, F64; },
  }
  }
 }

diff --git a/compiler/rustc_target/src/asm/mod.rs b/compiler/rustc_target/src/asm/mod.rs
@@ -176,6 +176,7 @@ pub enum InlineAsmArch {
  Nvptx64,
  Hexagon,
  Mips,
+ Mips64,
 }
 
 impl FromStr for InlineAsmArch {
@@ -192,6 +193,7 @@ impl FromStr for InlineAsmArch {
  "nvptx64" => Ok(Self::Nvptx64),
  "hexagon" => Ok(Self::Hexagon),
  "mips" => Ok(Self::Mips),
+ "mips64" => Ok(Self::Mips64),
  _ => Err(()),
  }
  }
@@ -259,7 +261,7 @@ impl InlineAsmReg {
  InlineAsmArch::Hexagon => {
  Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, target, &name)?)
  }
- InlineAsmArch::Mips => {
+ InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
  Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?)
  }
  })
@@ -409,7 +411,9 @@ impl InlineAsmRegClass {
  InlineAsmArch::Hexagon => {
  Self::Hexagon(HexagonInlineAsmRegClass::parse(arch, name)?)
  }
- InlineAsmArch::Mips => Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?),
+ InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
+ Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?)
+ }
  })
  })
  }
@@ -565,7 +569,7 @@ pub fn allocatable_registers(
  hexagon::fill_reg_map(arch, has_feature, target, &mut map);
  map
  }
- InlineAsmArch::Mips => {
+ InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
  let mut map = mips::regclass_map();
  mips::fill_reg_map(arch, has_feature, target, &mut map);
  map

diff --git a/src/doc/unstable-book/src/library-features/asm.md b/src/doc/unstable-book/src/library-features/asm.md
@@ -27,7 +27,7 @@ Inline assembly is currently supported on the following architectures:
 - RISC-V
 - NVPTX
 - Hexagon
-- MIPS32
+- MIPS32r2 and MIPS64r2
 
 ## Basic usage
 
@@ -513,8 +513,8 @@ Here is the list of currently supported register classes:
 | ARM | `qreg` | `q[0-15]` | `w` |
 | ARM | `qreg_low8` | `q[0-7]` | `t` |
 | ARM | `qreg_low4` | `q[0-3]` | `x` |
-| MIPS32 | `reg` | `$[2-25]` | `r` |
-| MIPS32 | `freg` | `$f[0-31]` | `f` |
+| MIPS | `reg` | `$[2-25]` | `r` |
+| MIPS | `freg` | `$f[0-31]` | `f` |
 | NVPTX | `reg16` | None\* | `h` |
 | NVPTX | `reg32` | None\* | `r` |
 | NVPTX | `reg64` | None\* | `l` |
@@ -552,6 +552,8 @@ Each register class has constraints on which value types they can be used with.
 | ARM | `qreg` | `neon` | `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4` |
 | MIPS32 | `reg` | None | `i8`, `i16`, `i32`, `f32` |
 | MIPS32 | `freg` | None | `f32`, `f64` |
+| MIPS64 | `reg` | None | `i8`, `i16`, `i32`, `i64`, `f32`, `f64` |
+| MIPS64 | `freg` | None | `f32`, `f64` |
 | NVPTX | `reg16` | None | `i8`, `i16` |
 | NVPTX | `reg32` | None | `i8`, `i16`, `i32`, `f32` |
 | NVPTX | `reg64` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
@@ -637,11 +639,11 @@ Some registers cannot be used for input or output operands:
 | x86 | `st([0-7])` | x87 registers are not currently supported (but may be in the future). |
 | AArch64 | `xzr` | This is a constant zero register which can't be modified. |
 | ARM | `pc` | This is the program counter, not a real register. |
-| MIPS32 | `$0` or `$zero` | This is a constant zero register which can't be modified. |
-| MIPS32 | `$1` or `$at` | Reserved for assembler. |
-| MIPS32 | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. |
-| MIPS32 | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. |
-| MIPS32 | `$ra` | Return address cannot be used as inputs or outputs. |
+| MIPS | `$0` or `$zero` | This is a constant zero register which can't be modified. |
+| MIPS | `$1` or `$at` | Reserved for assembler. |
+| MIPS | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. |
+| MIPS | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. |
+| MIPS | `$ra` | Return address cannot be used as inputs or outputs. |
 | RISC-V | `x0` | This is a constant zero register which can't be modified. |
 | RISC-V | `gp`, `tp` | These registers are reserved and cannot be used as inputs or outputs. |
 | Hexagon | `lr` | This is the link register which cannot be used as an input or output. |
@@ -689,8 +691,8 @@ The supported modifiers are a subset of LLVM's (and GCC's) [asm template argumen
 | ARM | `dreg` | None | `d0` | `P` |
 | ARM | `qreg` | None | `q0` | `q` |
 | ARM | `qreg` | `e` / `f` | `d0` / `d1` | `e` / `f` |
-| MIPS32 | `reg` | None | `$2` | None |
-| MIPS32 | `freg` | None | `$f0` | None |
+| MIPS | `reg` | None | `$2` | None |
+| MIPS | `freg` | None | `$f0` | None |
 | NVPTX | `reg16` | None | `rs0` | None |
 | NVPTX | `reg32` | None | `r0` | None |
 | NVPTX | `reg64` | None | `rd0` | None |