Verilog-Vivado

Digital Circuit Design using Verilog HDL (Hardware Description Language). Simulation was done on Xilinx Vivado IDE.

Name		Name	Last commit message	Last commit date
Latest commit History 50 Commits
4 Bit Magnitude Comparator		4 Bit Magnitude Comparator
4 Bit Multiplier		4 Bit Multiplier
Adder Subtractor		Adder Subtractor
BCD Adder		BCD Adder
Carry Look Ahead Adder (n bit)		Carry Look Ahead Adder (n bit)
Decoders		Decoders
Priority Encoder		Priority Encoder
Ripple Carry Adder (n bit)		Ripple Carry Adder (n bit)
Ripple Carry Adder		Ripple Carry Adder
Universal Shift Register		Universal Shift Register
Vedic Multiplier		Vedic Multiplier
F_Adder.v		F_Adder.v
H_Adder.v		H_Adder.v
README.md		README.md

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