Stars
Collect some CS textbooks for learning.
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
AISystem 主要是指AI系统,包括AI芯片、AI编译器、AI推理和训练框架等AI全栈底层技术
SystemVerilog grammar for tree-sitter
Rainbow delimiters for Neovim with Tree-sitter
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
High Contrast & Vivid Color Scheme based on Monokai Pro
verilog filetype plugin to enable emacs verilog-mode autos
Modern co-simulation framework for RISC-V CPUs
Verilog AXI components for FPGA implementation
A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
Random instruction generator for RISC-V processor verification
a training-target implementation of rv32im, designed to be simple and easy to understand
educational microarchitectures for risc-v isa
RSD: RISC-V Out-of-Order Superscalar Processor