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dh67-serial-debug.txt

@@ -0,0 +1,124 @@
+[!p[?3;4l>(B[?1h=(B[?12l[?25h[?25l                                                                                                               [?12l[?25h[?12l[?25h[?25lCTRL-A Z for help | 115200 8N1 | NOR | Minicom 2.8 | VT102 | Desconectado | ttyUSB0                            [?12l[?25h
+(BBem-vindo ao minicom 2.8
+
+OPÇÕES: I18n 
+Porta: /dev/ttyUSB0, 03:19:58
+
+Pressione CTRL-A Z para ajuda sobre teclas especiais
+
+reboot-24.02-410-g86b145ad3efe-dirty Thu Apr 04 03:26:19 UTC 2024 x86_32 bootblock starting (log level: 7)...
+[DEBUG] at 0x310000.
+[DEBUG]  F400000 #areas = 4
+[DEBUG]  FMAP: area COREBOOT found @ 310200 (982528 bytes)
+[ built for 16 files, used 0x354 of 0x4000 bytes
+[INFO ]  CBFS: Found 'fallback/romstage' @0x80 size 0x17670 in mcache 0xfeff0e2c
+[DEBUG]  BS:): total (unknown) / 46 ms
+
+
+(B[NOTE ]  coreboot-24.02-410-g86b145ad3efe-dirx86_32 romstage starting (log level: 7)...
+(B[DEBUG]  SMBERROR]  early_usb_init: USB04: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
+(B[ERROR]  early_usb_init: USB05: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
+[ERROR]  early_usb_init: USB06: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
+[ERROR]  early_usb_init: USB07: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
+[ERROlid setting for desktop!
+(B type: desktop
+[DEBUG]X4 @ 5000MT/s
+[DEBUG]  0m[DEBUG]  Selected DRAM frequen 10 us
+[DEBUG]  MPLL fr[DEBUG]  Done dimm mapping
+[DEBUG]  Update PCI-E cBUG]  PCI(0, 0, 0)[a0] = 80000000
+[DEBUG]  PCI(0, 0, 0)[a4] = 0
+[DEBUG]  PCI(0, 0, 0)[bc] = 7ea00000
+00
+[DEBUG]  PCI(0, 0, 0)[ac] = 1
+[DEBUG]  PCI(0, 0, 0)[b8] = 7c000000
+[DEBUG]  PCI(0, 0, 0)[b0] = 7ca00000
+[DEBUG]  PCI(0, 0, 0)[b4] = 7c800000
+[DEBUG]  PCI(0, 0, 0)[7c] = 7f
+[DEBUG]  PCI(0, 0, 0)[70] = 7f000000
+[DEBUG]  PCI(0, 0, 0)[74] = 0
+[DEBUG]  PCI(0, 0, 0)[78] = ff000c00
+[DEBUG]  Done memory mapvoke MEBx     : 0x0
+(B[NOME:  MFS failure     : 0x0(B
+  : 0x0
+(B[NOTE ]  ME:  Cte req   : 0x0(B
+(B[NOTE ]  ME:  (Reserved)      : 0x0(B
+(B[NOTE ]  ME:  Current state[NOTE ]  ME:  Progress code   : 0x1(B
+(B[NOTE ]  PASSED! Tell ME that DRAM is readyNOTE ]  ME:  Warm reset req  : 00x2c(B
+(B[NOTE ]  ME:  Curr0m
+[NOTE ]  ME: Requested Bth x8 single rank(B
+[DEBUenhanced interleave mode on
+[DEBUG]     rank interleave on
+[DEBUG]     DIMMA 2048 MB width x8 single rank root @ 0x7bffec00 62 entries.
+[DEBUG]  IMD: root @ 0DEBUG]  CBMEM entry for DIMM infe at 0x7bfce000 with entry 0x7bf postcar times (exec / console):  PCI: 00:00:02.0 [8086/0152] enabled
+[INFO ]  PCI: Stam
+[DEBUG]  PCI: 00:00:16.1 [8086/1c3b] disabled No operatiodevice
+[DEBUG]  PCI: 00:00:1c.3: Disabling device
+G]  PCI: 00:00:1f.6 [8086/1c24] disabled No operations
+evices:
+(B[WARN ]  PCI: 00:00:01.1(B
+(B[WARN ]  UMA and 2M GTT(B
+[DEBUG]  TSEG base 0x7c000000 size 8MG]  PCI: 00:00:16.2 register 14fffffff), read-only ignoring it
+[DEBUG]  PCI: 00:00:16.2 register 20(ffffffff), read-only ignoring it
+[DEBUG]fffff), read-only ignoring it
+[DEBUG]  PCI: 00:00:16.2 register 30(ffffffff), read-only ignoring it
+[DEBUG]  gnoring it
+[DEBUG]  PCIoring it
+[DEBUG]  PCI: placement) ===
+[DEBUG]   PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
+[DEBUG]   PCI: 00:00:1c.0f.3 20 base 00000400 limit 00000c *  [0xf000 - 0xffff] limit: ffff io
+[DEBUG]    PCI: 0] limit: efff io
+[DEBUGa0 - 0xefbf] limit: efbf io
+[DEBUG]    PCI: 00:00:1f.2 20 *  [0xef80 - 0xef9f] limit: ef9f io
+[DEBUG]    PCI:t: fdffffff
+[DEBUG]  DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff
+[DEBUG] [0m
+[INFO ]   * Base: f4000000, Size: a000000, Tag: 200
+[INFO ]   * Base: 10060000*  [0xfdad7000 - 0xfdad70ff] limit: fdad70ff mem
+[DEBUG]    PCI: 00:00:16.0 10 *  [0xfdad6000 - 0xfdad600f] limit: fda buprefmem
+[DEBUG]  PCI00000 gran 0x16 mem64
+[DEBUG]  PCI: 00:00:02.0 18 <- [0x00000000e0000000 - 0x00000000efffffff] size 0x10000000 gran 0x0000000000fffe] size 0x00000000 
+[DEBUG]  PCI: 00:02:00.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x0000000:1f.3 subsystem <- 8086/2001
+[DEBUG]  PCI: 00:00:1f.3 000e0000000 mask 0x0000000ff0000000 type 1
+[DEBUG]  MTR0m
+[DEBUG]  Fixed MTRRs   :]  CPU: APIC: 00 enabled
+
+[DEBUG]  CPU: APIC: 02UG]    ss0        [0x7c2fdc00-0x7c2fe000]
+[DEBUG]    st
+
+[DEBUG]  CPU 1EBUG]    stub1      [0x7c2f5c00 [0x7c2f5800-0x7c2f59a0]
+
+[DEBUG]  CPU 3
+[DEBUG]    ss3        [0x7c2fd000-0x7c2fd400]
+[DEBUG] alue of 0x7c2f6000
+[DEB2
+[DEBUG]  New SMBASE=0x7c2ed800 IEDBASE=0x7c400000
+[DEBUG]  Writing SMRR. base = 0x7c000006, mask=0xff800800S file
+(B[WARN ]  CBFS: 'pci8086,0106.rom' not found.            x_res x y_res: 1920   : NO(B
+[DEBUG]  ME: Update In Progress      : NO
+ State   : Initializing
+[DEBUG]  ME: Current Operation State : Bring up
+[DEBUG]  ME: Current Operation Mode  [0m
+[DEBUG]  ME: Power Manaue to exception
+[DEBUG]m
+[DEBUG]  PCI: 00:00:19.0 init
+[DEBUG]  PCI: 00:00:19.0 init finished in 0 msecs
+[DEBUG]  PCI: 00:00:1a: verb_size: 16
+[DEBUG] 10ec0892
+[DEBUG]  azal0:1b.0 init finished in 42 msecs
+[DEBUG]  PCI: 00:00:1clizing PCH PCIe bridge.
+ H67, device id: 0x1c4a, rev id 0x5
+[DEBUG]  IOAPIC: Initializing IOAPIC at fec00000
+[DEBUG]  IOAPIC: ID = 0CI: 00:00:1f.2 init finished in m[DEBUG]  PNP: 002e.b init
+urer: ef
+[INFO ]  SF: Dne.
+[INFO ]  Devices fiength now 84
+[INFO ]  ACPI: done.
+[DEBUG]  ACPI tables: 15056 bytes.
+e40000
+[DEBUG]  SMBIOS 
+[INFO ]  Create SMBIOS type 20
+[DEBUG]  SMBIOS tables: 838 bytes.
+[DEBUG]  Writing table forward entry 0m
+[DEBUG]   4. 000000007be40000-000000007be84fff: CONFIGURATION TABLES
+[DEBUG]   5. 000000007be85000-000000007bf000011b8d
+[DEBUG]  using LZMA[?25l+----------------------+|   Sair do Minicom?   ||               Não    |+----------------------+[?25l(B   Sim  [?12l[?25h(B[DEBUG]  PCI: 00:00:19.0 init                                        [DEBUG]  PCI: 00:00:19.0 init finished in 0 msecs                    [DEBUG]  PCI: 00:00:1a: verb_size: 16                                [DEBUG] 10ec0892                                                     [?12l[?25h[?12l[?25h[?12l[?25h[?1l>[!p[?3;4l>