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dh67gd/Kconfig

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+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_INTEL_DH67GD
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_4096
+	select GFX_GMA_ANALOG_I2C_HDMI_B
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select SUPERIO_WINBOND_W83667HG_A
+	select USE_NATIVE_RAMINIT
+
+
+config MAINBOARD_DIR
+	default "intel/dh67gd"
+
+config MAINBOARD_PART_NUMBER
+	default "DH67GD"
+
+endif
+

dh67gd/Kconfig.name

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+## SPDX-License-Identifier: GPL-2.0-or-later
+
+config BOARD_INTEL_DH67BL
+	bool "DH67GD"

dh67gd/Makefile.mk

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+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

dh67gd/acpi/ec.asl

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+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */

dh67gd/acpi/pci.asl

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+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Intel PCI to PCI bridge 0:1e.0 */
+
+Device (PCIB)
+{
+	Name (_ADR, 0x001E0000)
+
+	/* From vendor FW: Power Resources for Wake */
+	Name (_PRW, Package(){ 11, 4 })
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				/* PCI slot */
+				Package() { 0x0000ffff, 0, 0, 0x10 },
+				Package() { 0x0000ffff, 1, 0, 0x11 },
+				Package() { 0x0000ffff, 2, 0, 0x12 },
+				Package() { 0x0000ffff, 3, 0, 0x13 },
+
+				/* on-board IEEE1394 controller */
+				Package() { 0x0003ffff, 0, 0, 0x14 },
+			})
+		}
+		Return (Package() {
+			/* PCI slot */
+			Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+			/* on-board IEEE1394 controller */
+			Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+		})
+	}
+}

dh67gd/acpi/platform.asl

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+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+	Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}

dh67gd/acpi/superio.asl

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+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */

dh67gd/board_info.txt

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+Category: desktop
+Board URL: https://www.intel.com.br/content/www/br/pt/products/sku/50095/intel-desktop-board-dh67gd/specifications.html
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2011

dh67gd/cmos.default

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+## SPDX-License-Identifier: GPL-2.0-only
+boot_option=Fallback
+debug_level=Debug
+nmi=Disable
+power_on_after_fail=Disable
+sata_mode=AHCI
+gfx_uma_size=128M

dh67gd/cmos.layout

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+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	2	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	3	debug_level
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+
+409	2	e	4	power_on_after_fail
+411	2	e	5	sata_mode
+
+# coreboot config options: northbridge
+416	5	e	6	gfx_uma_size
+
+# coreboot config options: mainboard-specific
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID	value	text
+
+# Generic on/off enum
+1	0	Disable
+1	1	Enable
+
+# boot_option
+2	0	Fallback
+2	1	Normal
+
+# debug_level
+3	0	Emergency
+3	1	Alert
+3	2	Critical
+3	3	Error
+3	4	Warning
+3	5	Notice
+3	6	Info
+3	7	Debug
+3	8	Spew
+
+# power_on_after_fail
+4	0	Disable
+4	1	Enable
+4	2	Keep
+
+# sata_mode
+5	0	AHCI
+5	1	Compatible
+5	2	Legacy
+
+# gfx_uma_size (Intel IGP Video RAM size)
+6	0	32M
+6	1	64M
+6	2	96M
+6	3	128M
+6	4	160M
+6	5	192M
+6	6	224M
+6	7	256M
+6	8	288M
+6	9	320M
+6	10	352M
+6	11	384M
+6	12	416M
+6	13	448M
+6	14	480M
+6	15	512M
+6	16	1024M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 423 984

dh67gd/devicetree.cb

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+# SPDX-License-Identifier: GPL-2.0-or-later
+chip northbridge/intel/sandybridge
+	register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
+	device domain 0 on
+		subsystemid 0x8086 0x2001 inherit
+		device ref host_bridge on end	# Host bridge
+		device ref peg10 on end		# PEG
+		device ref peg11 off end 	# PEG11
+		device ref peg12 off end 	# PEG12
+		device ref igd on end		# iGPU
+		device ref dev4 off end 	# Device 4
+		device ref peg60 off end 	# PEG60
+
+		chip southbridge/intel/bd82x6x	# Intel Series 6 Cougar Point PCH
+			register "gen1_dec" = "0x000c0291"
+			register "sata_interface_speed_support" = "0x3"
+			register "sata_port_map" = "0x3f"
+			register "spi_lvscc" = "0x2005"
+			register "spi_uvscc" = "0x2005"
+
+			device ref mei1 on end		# Management Engine Interface 1
+			device ref me_ide_r off end	# Management Engine IDE-R
+			device ref me_kt off end	# Management Engine KT
+			device ref ehci2 on end		# USB2 EHCI #2
+			device ref gbe on # Intel Gigabit Ethernet
+				subsystemid 0x8086 0x2002
+			end		
+			device ref xhci off end		# USB3.0
+			device ref hda on end		# High Definition Audio
+			device ref pcie_rp1 on end	# PCIe Port #1
+			device ref pcie_rp2 on end	# PCIe Port #2 PCIe x1
+			device ref pcie_rp3 on end	# PCIe Port #3 PCIe x1
+			device ref pcie_rp4 on end	# PCIe Port #4 NEC USB 3.0
+			device ref pcie_rp5 on end	# PCIe Port #5
+			device ref ehci1 on end		# USB2 EHCI #1
+			device ref pci_bridge on end	# PCI bridge
+
+			device ref lpc on		# LPC bridge
+				chip superio/winbond/w83667hg-a	# Super I/O
+					device pnp 2e.0 off end		# FDC
+					device pnp 2e.1 off end		# LPT1
+					device pnp 2e.2 on		# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 off end		# COM2
+					device pnp 2e.5 off end		# PS/2 keyboard & mouse
+					device pnp 2e.106 on end	# SPI1 (Consumer Infrared?)
+					device pnp 2e.107 off end	# GPIO6
+					device pnp 2e.207 off end	# GPIO7
+					device pnp 2e.307 on		# GPIO8
+						irq 0xe4 = 0xfb
+						irq 0xe5 = 0x82
+					end
+					device pnp 2e.407 off end	# GPIO9
+					device pnp 2e.8 off end		# WDT
+					device pnp 2e.108 off end	# GPIO1
+					device pnp 2e.9 off end		# GPIO2
+					device pnp 2e.109 off end	# GPIO3
+					device pnp 2e.209 on		# GPIO4
+						irq 0xf0 = 0xff
+						irq 0xfe = 0x07
+					end
+					device pnp 2e.309 off end	# GPIO5
+					device pnp 2e.a on end		# ACPI
+					device pnp 2e.b on		# HW Monitor
+						io 0x60 = 0x290
+						irq 0x70 = 0
+					end
+					device pnp 2e.c on end		# PECI
+					device pnp 2e.d on end		# VID_BUSSEL
+					device pnp 2e.f on end		# GPIO_PP_OD
+				end
+			end
+			device ref sata1 on end		# SATA (AHCI)
+			device ref sata2 off end 	# SATA (Legacy)
+			device ref smbus on end		# SMBus
+		end
+	end
+end

dh67gd/dsdt.asl

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+		#include "acpi/pci.asl"
+	}
+}

dh67gd/early_init.c

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/winbond/w83667hg-a/w83667hg-a.h>
+#include <superio/winbond/common/winbond.h>
+#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, 0 },
+	{ 1, 0, 0 },
+	{ 1, 0, 1 },
+	{ 1, 0, 1 },
+	{ 1, 0, 2 },
+	{ 1, 0, 2 },
+	{ 1, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 0, 4 },
+	{ 1, 0, 4 },
+	{ 1, 0, 6 },
+	{ 1, 0, 5 },
+	{ 1, 0, 5 },
+	{ 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}

dh67gd/gma-mainboard.ads

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+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      DP3,
+      HDMI1,
+      HDMI2,
+      HDMI3,
+      Analog,
+     others => Disabled);
+
+end GMA.Mainboard;