Console application for apply format to verilog file.
Application options:
usage: [java -jar verilog-format.jar|./verilog-format|verilog-format.exe]
[-f <pathname>] [-h] [-p] [-s <verilog-format.properties>] [-v]
-f,--format <pathname> verilog file
-h,--help print this message
-p,--print print file formated
-s,--settings <verilog-format.properties> settings config
-v,--version verilog-format version
## Print input_file.v formatted
$ ./verilog-format -p -f input_file.v -s verilog-format.properties
## Format input_file.v
$ ./verilog-format -f input_file.v -s verilog-format.properties
## Format input_file.v
## If .verilog-format.properties exist in project folder, this is used,
## otherwise default setting is used..
$ ./verilog-format -f input_file.v
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Clone repository.
$ git clone https://github.com/ericsonj/verilog-format.git -
Install verilog-format
$ cd verilog-format/bin/
$ sudo mkdir /opt/verilog-format
$ sudo unzip verilog-format-LINUX.zip -d /opt/verilog-format/ -
Execute like java
$ java -jar /opt/verilog-format/verilog-format.jar -
Execute like linux script
$ /opt/verilog-format/verilog-format -
Install in system
$ sudo cp /opt/verilog-format/verilog-format /usr/bin/
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Clone repository or download verilog-format-WIN.zip
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Unzip and copy in your preferer folder.
For build de project, Maven is needed.
$ cd verilog-format
$ mvn clean package
$ ls target/
This options are setting in .verilog-format.properties file.
## File .verilog-format.properties
IndentWidth=4
IndentType=space
SpacesBeforeTrailingComments=0
SpacesAfterTrailingComments=0
AlignLineComments=true
AlignNoBlockingAssignments=true
AlignBlockingAssignments=true
SpacesInParentheses=false
SpacesInSquareBrackets=false// IndentWidth=4 #(default)
always @(posedge clk)
if (load == 1)
bitc <= 0;
else if (load == 0 && clk_baud == 1)
bitc <= bitc + 1;
// IndentWidth=1
always @(posedge clk)
if (load == 1)
bitc <= 0;
else if (load == 0 && clk_baud == 1)
bitc <= bitc + 1;// IndentType=space #(default)
always @(posedge clk)
if (load == 1)
bitc <= 0;
else if (load == 0 && clk_baud == 1)
bitc <= bitc + 1;
// IndentType=tab # not recommended yet
always @(posedge clk)
<tab>if (load == 1)
<tab><tab>bitc <= 0;
<tab>else if (load == 0 && clk_baud == 1)
<tab><tab>bitc <= bitc + 1;// SpacesInParentheses=false #(default)
always @(posedge clk)
if (load == 1)
// SpacesInParentheses=true
always @( posedge clk )
if ( load == 1 )// SpacesInSquareBrackets=false #(default)
reg [DW-1:0] rom [0:NPOS-1];
always @(posedge clk) begin
data <= rom[addr];
end
// SpacesInSquareBrackets=true
reg [ DW-1:0 ] rom [ 0:NPOS-1 ];
always @(posedge clk) begin
data <= rom[ addr ];// AlignBlockingAssignments=true #(default)
assign load = (state == START) ? 1 : 0;
assign baud_en = (state == IDLE) ? 0 : 1;
// AlignBlockingAssignments=false
assign load = (state == START) ? 1 : 0;
assign baud_en = (state == IDLE) ? 0 : 1;
// AlignNoBlockingAssignments=true #(default)
state_ts <= IDLE;
state_pad <= IDLE;
state_wait <= IDLE;
// AlignNoBlockingAssignments=false
state_ts <= IDLE;
state_pad <= IDLE;
state_wait <= IDLE;// AlignLineComments=false #(default)
always @(posedge clk) // always
if (load == 1) // if
bitc <= 0; //
else if (load == 0 && clk_baud == 1) // else if
bitc <= bitc + 1; //
// AlignLineComments=true
always @(posedge clk) // always
if (load == 1) // if
bitc <= 0; //
else if (load == 0 && clk_baud == 1) // else if
bitc <= bitc + 1; //// SpacesBeforeTrailingComments=1 #(default)
localparam IDLE = 0; //IDLE
// SpacesBeforeTrailingComments=0
localparam IDLE = 0;//IDLE// SpacesAfterTrailingComments=0 #(default)
localparam IDLE = 0; //IDLE
// SpacesAfterTrailingComments=3
localparam IDLE = 0; // IDLE