Simulate logic gates on a compiled single-instruction VM with Rust.

I wanted to build a system to work with a known-system rather than interpreting the circuit graph each tick, even if it was lazy. With Complogic, all gates are compiled into a set of Nand instructions, which execute at runtime.

With this design decision comes the power to ignore propagation entirely and set everything all at once. There isn't any "run until things settle" logic, and the system is entirely deterministic.

The VM only cares about outputs. Inputs are immediates, provided when running the simulation. Any gate that needs an input, can either use the output of another gate, or the immediates. This allows everything to be packed within the register stack of the VM, only storing the necessary values.

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