Classic single-issue five-stage pipelined MIPS CPU with TLB support. The master branch was used as submission to NSCSCC 2020, a national competition on computer systems and architecture.
Implements around 80 MIPS instructions and all required CP0 registers in MIPSr1 (however some of the implementations are adjusted to suit the needs of the competition). Please refer to FDU1.2.pdf, FDU1.2.pptx and score_final.xls for more details.
The dual-issue branch consists of a simple dual-issue five-stage CPU without TLB support. It comes with a higher IPC but lower frequency (~70 MHz).