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Fully self-learnt freelancer interested in low-level languages, embedded systems, hardware design, and artificial intelligence.
- United States of America
- https://thraetaona.github.io/
- https://orcid.org/0000-0003-1393-6804
Highlights
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A Simple VHDL Abstraction of an Effi...
A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers 1-------------------------------------------------------------------------------
2-- SPDX-License-Identifier: LGPL-3.0-or-later or CERN-OHL-W-2.0
3--
4-- srl_prescaler.vhd: A Simple VHDL Abstraction of an Efficient Clock
5-- Prescaler Using Cascading Shift Registers.
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