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A Fully Open-Source Verilog-to-PCB Flow
Python 13 2
Minimal SoC containing a Serv-RV32I Core designed for usage with Liberty74
Verilog 2
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
SystemVerilog 83 24
Forked from The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Verilog
