This project aims to evaluate 4 basic microarchitectures for RV32I base ISA.

1. Single-cycle
2. Multi-cycle
3. 5-staged pipeline (no data forwarding)
4. 5-staged pipeline (with data forwarding)

The repo is organized as follows:

• Images : Block diagrams of microarchitectures
• PyRV32I : A tiny python based riscv emulator (https://github.com/vithurson/PyRV32I)
• rtl : Contains all the RTL files and verilator drivers
• testcase_gen : RV32I ISA random test cases generator (https://github.com/Amrsaeed/riscv_test_generator)

This project uses verilator for simulation and PyRV32I as the compiler for C programs.

• First clone the RV32I Core

git clone https://github.com/SachiniW/RISC-V_Processor.git

• The RV32I instructions for a basic C code is added to the repo as rtl/src/instruction_memory.mem. To run the simulation the default C code,

cd RISC-V Processor/rtl/src
./run.sh

• Simulation can be carried out in 3 paths

  1. Simulation using 5-staged pipelined design with the default C code in the memory.

     ./run.sh
     

     

  2. Simulation using a selected design with the default C code in the memory.

     ./run.sh eval
     

     

  3. Simulation using a selected design with a custom C code in the memory.

     • To execute this command toolchain should be present in PyRV32I/toolChain folder.
     • Download tool chain from https://github.com/stnolting/riscv-gcc-prebuilt/releases/download/rv32i-2.0.0/riscv32-unknown-elf.gcc-10.2.0.rv32i.ilp32.newlib.tar.gz
     • Extract and put the contents into toolChain folder

     ./run.sh eval new
     

     

  4. The program's output is as follows.

     

The project was initially intended to support synthesis on FPGAs. Hence, the current designs have been synthesized but have not been tested in hardware.

• Verilog modules : rtl/src/
• Testbenches : rtl/tb/

• Testing on hardware