Release of X-CUBE-AZRTOS-L4 v2.0.0

Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h

@@ -7,18 +7,17 @@
  * This file contains:
  * - Data structures and the address mapping for all peripherals
  * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral�s registers hardware
+ * - Macros to access peripheral's registers hardware
  *
  ******************************************************************************
  * @attention
  *
- * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
  *
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */
@@ -45,11 +44,11 @@
 /**
  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
  */
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
 
 /**
  * @}
@@ -1011,6 +1010,15 @@ typedef struct
  * @{
  */
 
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
 /** @addtogroup Peripheral_Registers_Bits_Definition
  * @{
  */
@@ -1161,7 +1169,7 @@ typedef struct
 
 #define ADC_CFGR_ALIGN_Pos (5U)
 #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
 
 #define ADC_CFGR_EXTSEL_Pos (6U)
 #define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -10910,4 +10918,3 @@ typedef struct
  * @}
  */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/