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RexJian/README.md

Hi I'm Rex Jian ๐Ÿ‘‹

  • ๐Ÿ˜„ I am currently pursuing my masterโ€™s degree in Electrical Engineering at Chung Cheng University
  • ๐ŸŒฑ Iโ€™m learning Digital IC Design / Verification

๐Ÿ’ก Projects

Digital IC Verification

Digital IC Design

MCU & Machine Learning

๐Ÿ“š Skills

Digital IC Verification

  1. Develop integrated verification environment with SystemVerilog
  2. Use random stimulus with functional coverage

Digital IC Desgin

  1. RTL coding, STA, Synthesis
  2. Gate level to Post- Layout simulation and Cell based APR flow

๐Ÿ”ง Languages

SystemVerilog

Verilog

C/C++

Python

TCL

Some Statistics About Me

Top Langs

Popular repositories Loading

  1. ESP32_NeuralNetwork ESP32_NeuralNetwork Public

    Create a basic neural network that can recognize numbers from 0 to 9 and use it as a calculator.

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  2. LCD-Image-Controller LCD-Image-Controller Public

    The main purpose of the circuit is to process an 8x8 grayscale image using a series of predefined commands that alter the display in different ways.

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  3. RexJian RexJian Public

    HomePage

  4. SystemVerilogLabs SystemVerilogLabs Public

    Construct a typical architecture of a SystemVerilog testbench

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  5. Using-standard-cell-compare-triangle-areas Using-standard-cell-compare-triangle-areas Public

    Calculate the areas of two triangles, the circuits outputs the larger triangle's area and its hypotenuse's length

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  6. Convolution-Circuit Convolution-Circuit Public

    In the lab, I am working on designing a circuit that conducts a sequence of convolution operations on an input image, followed by applying the RELU activation function. More specifically, I have imโ€ฆ

    Verilog