Skip to content
@RISCVNexus

RISCVNexus

Popular repositories Loading

  1. etiss_riscv_examples etiss_riscv_examples Public

    Forked from tum-ei-eda/etiss_riscv_examples

    C

  2. softvector softvector Public

    Forked from tum-ei-eda/softvector

    Vector arithmetic library targeting simulation of Vector Processing Units (VPUs) for various targets, e.g., ETISS.

    C++

  3. muriscv-nn muriscv-nn Public

    Forked from tum-ei-eda/muriscv-nn

    muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.

    C++

  4. rvdbg rvdbg Public

    Forked from deadsy/rvdbg

    RISC-V Debugger

    Go

  5. pyocdriscv32 pyocdriscv32 Public

    Forked from michg/pyocdriscv32

    Python script for controlling the debug-jtag port of riscv cores

    Verilog

  6. rv-link rv-link Public

    Forked from michahoiting/rv-link

    RV-Link: In application debugger for RISC-V micro-controllers, RISC-V emulator, running on RISC-V development boards (e.g. Sipeed Longan Nano or GD32VF103C-START).

    C

Repositories

Showing 10 of 44 repositories
  • riscv-profiles Public Forked from riscv/riscv-profiles

    RISC-V Architecture Profiles

    RISCVNexus/riscv-profiles’s past year of commit activity
    Makefile 0 CC-BY-4.0 33 0 0 Updated Oct 28, 2024
  • e203_hbirdv2 Public Forked from riscv-mcu/e203_hbirdv2

    The Ultra-Low Power RISC-V Core

    RISCVNexus/e203_hbirdv2’s past year of commit activity
    Verilog 0 Apache-2.0 343 0 0 Updated Oct 24, 2024
  • BRISKI Public Forked from riadhbenabdelhamid/BRISKI

    BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput and compute density to increase the amount of cores in many-core design without sacrificing performance.

    RISCVNexus/BRISKI’s past year of commit activity
    SystemVerilog 0 Apache-2.0 4 0 0 Updated Oct 10, 2024
  • meta-riscv Public Forked from riscv/meta-riscv

    OpenEmbedded/Yocto layer for RISC-V Architecture

    RISCVNexus/meta-riscv’s past year of commit activity
    BitBake 0 141 0 0 Updated Sep 21, 2024
  • riscv-tflite Public Forked from fabrizioaymone/riscv-tflite

    This repo evaluates TensorFlow Lite for Microcontrollers (TFLite Micro) on RISC-V architectures, featuring cross-compilation and performance profiling with Spike and Gem5. It provides insights into in-order vs. out-of-order core designs for TinyML workloads.

    RISCVNexus/riscv-tflite’s past year of commit activity
    C++ 0 MIT 1 0 0 Updated Sep 9, 2024
  • DBT-RISE-RISCV Public Forked from Minres/DBT-RISE-RISCV

    An instruction set simulator based on DBT-RISE implementing the RISC-V ISA

    RISCVNexus/DBT-RISE-RISCV’s past year of commit activity
    C 0 BSD-3-Clause 15 0 0 Updated Aug 28, 2024
  • t1 Public Forked from chipsalliance/t1
    RISCVNexus/t1’s past year of commit activity
    Scala 0 Apache-2.0 23 0 0 Updated Aug 16, 2024
  • sail-riscv Public Forked from riscv/sail-riscv

    Sail RISC-V model

    RISCVNexus/sail-riscv’s past year of commit activity
    Coq 0 166 0 0 Updated Aug 13, 2024
  • cheshire Public Forked from pulp-platform/cheshire

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

    RISCVNexus/cheshire’s past year of commit activity
    Verilog 0 46 0 0 Updated Aug 1, 2024
  • pinwheel Public Forked from aappleby/pinwheel

    A tiny RISC-V processor for hard-real-time FPGA-based applications.

    RISCVNexus/pinwheel’s past year of commit activity
    Verilog 0 1 0 0 Updated Jul 31, 2024
View all repositories

People

This organization has no public members. You must be a member to see who’s a part of this organization.

Top languages

Loading…

Most used topics

Loading…