Process Design Kit (PDK) is a set of files or models used within the semiconductor industry to model a fabrication process characteristic for the design tools and its users used to design an integrated circuit. An accurate PDK will increase the chances of first-pass successful silicon and provide good yield for chip.

The OpenRPDK28 is Open RIOS PDK, created by the RIOS Lab. This PDK is open-source and could be used for a preliminary template for the industrial level PDK. The OpenRPDK28 is an open-source PDK developed by the RIOS Lab and serves as a preliminary template for industrial-level PDKs. The PDK is designed to be flexible and customizable, allowing users to modify it to their specific needs. Additionally, the OpenRPDK28 offers a wide range of features, such as the ability to integrate with open-source EDA tools. The PDK is also accompanied by comprehensive documentation, making it easy for users to get started and begin designing their own chips. Overall, the OpenRPDK28 will be an excellent choice for anyone looking to develop their own custom chips and is sure to meet the needs of a wide range of users.

As part of its commitment to the open-source community, RIOS Lab will make the OpenRPDK28 project completely open-source. This means that anyone can access the code, contribute to the project, and even use this pDK in their own products. RIOS Lab believes that by making the project open-source, it will encourage innovation and collaboration in the process-design bridge, leading to even more exciting and groundbreaking developments in the future.

28nm OpenRPDK Content

OpenRPDK28 is under constrcuction now

OpenRPDK28 defines a certain technology variation and characteristic for the 28nm open-source academic processes. Designers may enhance this PDK, tailoring it to their specific design styles and markets.

OpenRPDK28 offers a library of blocks for re-use, each one the result of years of research and development. It will plays a pivotal role in open source EDA and process breakthrough:

1. Access to a OpenRPDK28 means IC designers don’t have to start from scratch. Designer could choose from open-source building blocks which have already proven their efficacy and functionality, resulting in a shorter time to research or market and at lower development costs.

2. An OpenRPDK28 is crucial in the design phase. 28nm PDK-based designs follow a series of design rules which makes them compliant with 28nm open-source process.

Designers could use the OpenRPDK28 to design, simulate, draw and verify the integrated circuit design before puting the design back to the foundry to manufacture chips.

Open EDA Ecosystem

Different tools in the design flow have different input formats for the PDK data.

OpenRPDK28 PDK contains:

• Technology data

  • Layers, layer names, layer/purpose pairs

  • Colors, fills and display attributes

  • Process constraints

  • Electrical rules

• A primitive device library

  • Symbols

  • SPICE or Varilog-A model and device parameters

  • Parameterized cells

• Rule check files

  • Design rule checking

  • Layout versus schematic

  • Antenna and electrical rule check

  • Physical parameters extraction

  • Litho friendly check

  • Other DFM check

• Design Rule Manual

  • A user friendly documents of the process

Standard Cell Designed with OpenRPDK

Design Technology Co-Optimization (DTCO) is a methodology that helps semiconductor foundries reduce cost and time-to-market in process development.

In DTCO flow, design and process technology optimized together to improve performance, power efficiency, transistor density, and cost. DTCO for a new technology node usually involves substantial architectural innovation instead of just delivering the similar structure as the previous process node.

DTCO Flow (Source: Synopsys)

As the IC manufacturing enter sub 40nm tech nodes, DFM become more and more important to make sure more stable yield and lower cost. Manufacturing is facing big challenges in terms of manufacturability, yield ramp-up, and variability.

To addresses these challenges, physical verification and implementation technolgies have been augmented with in-design and signoff DFM checks and automated DFM enhancement, then designers can reduce the impact of variability and improve the manufacturability of IC designs. And foundries also need highly accurate modeling and efficient design analysis, yield enhancements, and mask data preparation in their workflow.

Typical DFM flow:

1. LFD (Litho Fridenly Design)

LFD is the methodology to address the urgent issue of how to accurate manage lithographic process variability in the early stages of design creation. Accurately LFD could maintain the lithographic processes on “as-drawn” layout data to determine the actual “as-built” dimensions of fabricated gates and metal interconnects.

2. CMP(Chemical-mechanical polishing)

Chemical mechanical polishing (CMP) or planarization is a process of smoothing surfaces with the combination of chemical and mechanical forces. It can be thought of as a hybrid of chemical etching and free abrasive polishing

Multi-physics and IR-Drop analysis are important steps in designing electronic chips. Multi-physics analysis allows you to simulate how your chip behaves under different conditions, giving you insight into its performance. This helps you identify potential problems and make improvements before manufacturing. Similarly, IR-Drop analysis ensures that your chip is optimized for power delivery and voltage drops. By analyzing voltage drop across the chip, you can identify areas where voltage may be too low and take steps to fix it. Combining both analyses improves the manufacturability, performance, and reliability of your chip. It's worth noting that while these analyses may add complexity to the design process, their long-term benefits outweigh any drawbacks.

Furthermore, when considering the manufacturing cost and time of a product, it is important to take into account changes in multi-physics and IR-drop. Multi-physics refers to the interaction of different physical phenomena in a manufacturing process, such as thermo-mechanical or electro-thermal interactions. Changes in multi-physics can have a significant impact on the manufacturability of a product and need to be considered during the design phase. Similarly, IR-drop refers to the voltage drop across a circuit due to the resistance of the materials used. This can lead to a significant reduction in power and performance of the device being manufactured. By taking into account changes in multi-physics and IR-drop, engineers and designers can make more informed decisions that will ultimately result in a more robust and efficient manufacturing process.

Under the guidance of Moore's Law, the feature length of integrated circuits is constantly reducing.

The 28nm process is between 32nm and 22nm. 2013 was the year of 28nm process popularization. Between 2015 and 2016, the 28nm process began to be used in cell phone application processors and basebands chip at scale.

The planar process can be most cost-effective at 28nm, and 28nm maybe the best planar process in foundry both in performance and cost-efficiency . For the subsequent 16/14nm FinFET process, the cost of IC manufacturing increases by at least 50%. Only applications with huge amount such as cell phones or processors can support the cost and market size. In many applications, 28nm planar process offers good value for performance, and cost balance.

28nm HP 6T-SRAM Example – Plan View SEM (Source: chipworks)

Ecosystem Wants to be Free

By David A. Patterson · Director of RIOS Lab

RISC-V International Open Source Laboratory (RIOS Lab) is a Shenzhen-based research facility focused on computer system architecture, supported by the Tsinghua-Berkeley Shenzhen Research Institute. As an Open Source and Nobel Prize Laboratory, RIOS Lab promotes open-source innovation and collaboration. Our philosophy is that the computer architecture ecosystem should be free for all to access and build upon.

In November 2019, RIOS Lab was officially unveiled. Under the leadership of 2017 A.M. Turing Award winner Prof. David A. Patterson and operational support from TBSI, RIOS Lab will conduct cutting-edge research in RISC-V hardware and software technology. Patterson first proposed the Reduced Instruction Set Computer (RISC), an open and free instruction set architecture enabling a new era of processor innovation through open standard collaboration. Released in 2010, the latest Fifth Generation RISC has gained worldwide attention.

The name for the lab RIOS is also inspired by the Spanish word for “rivers.” It symbolizes the flow of information from many sources, coming together to create a whole that is greater than the sum of its parts.