Skip to content
View NickolayTernovoy's full-sized avatar
👽
PhD student at MIET; RISC-V, Posit enthusiast;
👽
PhD student at MIET; RISC-V, Posit enthusiast;

Block or report NickolayTernovoy

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. risc-v_awesome_list risc-v_awesome_list Public

    47

  2. SimpleCacheController SimpleCacheController Public

    Advanced Material: Implementing Cache Controllers

    SystemVerilog

  3. mdu mdu Public

    Forked from zeeshanrafique23/mdu

    M-extension for RISC-V cores.

    Verilog

  4. schoolRISCV schoolRISCV Public

    Forked from zhelnio/schoolRISCV

    CPU microarchitecture, step by step

    Makefile 1

  5. schoolRISCV_ICache schoolRISCV_ICache Public

    Академический проект для исследования прироста производительности процессора в зависимости от конфигурации Иерархии Памяти

    Makefile 6 3