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Starred repositories
Сross-platform software for keeping your notes in a tree
Render Wavedrom diagrams in you Joplin notes.
GoodbyeDPI — Deep Packet Inspection circumvention utility (for Windows)
Небольшое расширение, которое добавляет закадровый перевод видео из YaBrowser в другие браузеры
Основы программной инженерии (SWEBOK 2004 на русском) в EPUB, FB2 и HTML
cloc counts blank lines, comment lines, and physical lines of source code in many programming languages.
Python productivity for RFSoC platforms
A one-of-a-kind resume builder that keeps your privacy in mind. Completely secure, customizable, portable, open-source and free forever. Try it out today!
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…
PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
A simple implementation of a UART modem in Verilog.
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first …
Репозиторий факультатива по функциональной верификации НИУ МИЭТ
🇯 JSON encoder and decoder in pure SystemVerilog
AMBA bus generator including AXI4, AXI3, AHB, and APB
synthesiseable ieee 754 floating point library in verilog