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1. Spartan6-DSP48A1-FPGAs Spartan6-DSP48A1-FPGAs Public

   Simulated and implemented the DSP48A1 slice from the Spartan-6 family. o Tools/Technologies Used: Verilog HDL – Questa sim – VIVADO.

   Verilog

2. SPI-Slave-connected-to-single-Port-RAM.- SPI-Slave-connected-to-single-Port-RAM.- Public

   Implemented an SPI slave which interfaced with dual port memory and complete testbench. o Tools/Technologies Used: Verilog HDL – Questa sim.

   VHDL

3. FIFO-and-a-complete-top-level-UVM-environment-for-SPI-Slave-connected-to-single-port-RAM. FIFO-and-a-complete-top-level-UVM-environment-for-SPI-Slave-connected-to-single-port-RAM. Public

   Designed and Verified FIFO and its functionality using a complete top level UVM environment Testbench. o Tools/Technologies Used: System Verilog – Assertion – Questa sim.

   SystemVerilog

4. Developed-a-complete-top-level-UVM-environment-for-Shift-Reg Developed-a-complete-top-level-UVM-environment-for-Shift-Reg Public

   SystemVerilog

5. Single-Carrier-Communication-systems Single-Carrier-Communication-systems Public

   About It has multiply codes that model different communications systems, like DSB-SC, BPSK, QPSK ,8PSK,16-QAM and BFSK using MATLAB

   MATLAB

6. Matched-Filters-Correlators-ISI-and-raised-cosine-filters Matched-Filters-Correlators-ISI-and-raised-cosine-filters Public

   Matched filters and correlators optimize signal detection and similarity measurement in noisy environments, essential for communication systems. Raised cosine filters shape signals to minimize inte…

   MATLAB