Skip to content

Configurable real time clock on the Terasic DE0-CV board, using VHDL and custom ASM code

Notifications You must be signed in to change notification settings

MekhyW/FPGA-Clock

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

27 Commits
 
 
 
 
 
 
 
 

Repository files navigation

FPGA-Clock

About

Configurable real time clock on the Terasic DE0-CV board, using VHDL and custom ASM code

Topics

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages